时序测试

测试向量功能支持组合和时序电路测试。默认情况下，测试是组合的：每个测试前都会重置电路，确保每个测试都是独立的。

对于时序电路，您可以使用特殊的 <set>和<seq> 标题列来指定测试序列：

<set>：定义序列 ID - 具有相同集合编号的测试属于同一序列并一起运行。同一集合中的步骤之间会保留电路状态。如果未指定，测试默认为集合 0。
<seq>：定义集合内的步骤编号 - 这决定了同一集合内测试的执行顺序。测试按照每个 <set> 内的 <seq> 值顺序执行。<seq> 为 0 或缺失的测试被视为组合测试（测试之间重置电路，即使它们共享同一集合）。

以下是时序测试向量的示例：

# 计数器的时序测试
Clock Reset Count <set> <seq>
0     0     0     1     1
1     0     0     1     2
0     0     1     1     3
1     0     1     1     4
0     0     2     1     5
1     0     2     1     6
0     1     0     2     1

在此示例中，前六个测试都具有 <set> 1 和 <seq> 值 1-6，因此它们形成一个按顺序运行的序列（seq 1，然后是 2，然后是 3，等等），步骤之间不重置。最后一个测试具有 <set> 2，因此它开始一个新序列，并在运行前重置电路。

Note also that Clock could be an input pin here. But it could also be a labeled clock component (see below).

序列执行规则

具有相同 <set> (> 0) 编号的测试属于同一序列
在每个集合内，测试按其 <seq> 值顺序执行（seq 1，然后是 2，然后是 3，等等）
The circuit state is maintained between tests in the same set (same set ID)
开始新集合（不同的 <set> 编号）时会重置电路
Tests with <seq> = 0 or missing must also have <set> = 0 or missing and are always combinational (reset between tests)

Using the Clock

In a sequential test, the first step begins with a reset. In every step after the first, it begins with a simulation tick. Any Clock components in the simulation will be updated by that tick and their signals will be propagated along with any input pin values for that step. You may add a column to the test to show the ticks. The column will be checked against the clock in the circuit as if it were an output pin to verify it describes the clocks behavior. Here is an example for a simple positive edge-triggered D flip-flop test with a standard clock:

<clk> D Q NotQ  <set> <seq>
  0   0 0   1     1     1
  1   0 0   1     1     2
  0   1 0   1     1     3
  1   1 1   0     1     4
  0   1 1   0     1     5
  1   1 1   0     1     6
  0   0 1   0     1     7

The <clk> header is a special name for an unlabeled clock component. You may also label the clock and use the label as the column header (see earlier example).

We recommend that when using a Clock, you should not change the values of memory inputs during the same step that the clock makes a triggering transition. Doing so may allow an input signal to reach the component at near the same time as the clock signal giving surprising behavior. In the example above, the D input does not change in steps with a rising edge of the clock.

完整示例

以下是结合所有功能的完整示例：

# Mixed combinational and sequential tests
A B C Out     <clk> <set> <seq>
0 0 0 0       0     0     0
0 0 1 1       0     0     0
1 1 0 1       0     1     1
0 1 0 0       1     1     2
1 1 1 1       0     1     3
0 0 0 <DC>    0     2     1
1 0 1 <float> 1     2     2

In this example:

Notice how the clock resets to 0 in each line that does a reset.
The first two tests are combinational (seq=0), so the circuit resets between each test, even though they share set 0.
The next three tests all have set 1 with seq values 1-3, so they form one sequence that runs in order without reset between each other only resetting before the first test in the set runs.
The last test has set 2 seq 1&2, so it starts a new sequence and the circuit resets before it runs but not between tests in the set.
The sixth test uses <DC> for the output, so any output value passes.
The last test uses <float> for the output, expecting a floating value.

Thus the execution might look like this:

Reset, set A=0, B=0, C=0 and check that Out==0 and clk=0
Reset, set A=0, B=0, C=1 and check that Out==1 and clk=0
Reset, set A=1, B=1, C=0 and check that Out==1 and clk=0
Tick, set A=0, B=1, C=0 and check that Out==0 and clk=1
Tick, set A=1, B=1, C=1 and check that Out==1 and clk=0
Reset, set A=0, B=0, C=0 and not check Out but clk=0
Tick, set A=1, B=0, C=1 and check that Out is floating (in Logisim this is notated as U) and clk=1
Test Vector is complete

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