Sequential Testing

The Test Vector feature supports both combinational and sequential circuit testing. By default, tests are combinational: the circuit is reset before each test, ensuring each test is independent.

For sequential circuits, you can specify test sequences using the special <set> and <seq> header columns:

• <set>: Defines the sequence ID - tests with the same set number belong to the same sequence and run together. The circuit state is preserved between steps in the same set. Tests default to set 0 if not specified.
• <seq>: Defines the step number within a set - this determines the execution order of tests within the same set. Tests are executed in order of their <seq> value within each <set>. Tests with <seq> of 0 or missing are treated as combinational (circuit resets between tests, even if they share the same set).

Here is an example of a sequential test vector:

# Sequential test for a counter
Clock Reset Count <set> <seq>
0     0     0     1     1
1     0     0     1     2
0     0     1     1     3
1     0     1     1     4
0     0     2     1     5
1     0     2     1     6
0     1     0     2     1

In this example, the first six tests all have <set> 1 with <seq> values 1-6, so they form one sequence that runs in order (seq 1, then 2, then 3, etc.) without resetting between steps. The last test has <set> 2, so it starts a new sequence and the circuit is reset before it runs.

Note also that Clock could be an input pin here. But it could also be a labeled clock component (see below).

Sequence Execution Rules

• Tests with the same <set> number (> 0) belong to the same sequence.
• Within each set, tests are executed in order of their <seq> value (seq 1, then 2, then 3, etc.)
• The circuit state is maintained between tests in the same set (same set ID)
• The circuit is reset when starting a new set (different <set> number)
• Tests with <seq> = 0 or missing must also have <set> = 0 or missing and are always combinational (reset between tests)

Using the Clock

In a sequential test, the first step begins with a reset. In every step after the first, it begins with a simulation tick. Any Clock components in the simulation will be updated by that tick and their signals will be propagated along with any input pin values for that step. You may add a column to the test to show the ticks. The column will be checked against the clock in the circuit as if it were an output pin to verify it describes the clocks behavior. Here is an example for a simple positive edge-triggered D flip-flop test with a standard clock:

<clk> D Q NotQ  <set> <seq>
  0   0 0   1     1     1
  1   0 0   1     1     2
  0   1 0   1     1     3
  1   1 1   0     1     4
  0   1 1   0     1     5
  1   1 1   0     1     6
  0   0 1   0     1     7

The <clk> header is a special name for an unlabeled clock component. You may also label the clock and use the label as the column header (see earlier example).

We recommend that when using a Clock, you should not change the values of memory inputs during the same step that the clock makes a triggering transition. Doing so may allow an input signal to reach the component at near the same time as the clock signal giving surprising behavior. In the example above, the D input does not change in steps with a rising edge of the clock.

Complete Example

Here is a complete example combining all features:

# Mixed combinational and sequential tests
A B C Out     <clk> <set> <seq>
0 0 0 0       0     0     0
0 0 1 1       0     0     0
1 1 0 1       0     1     1
0 1 0 0       1     1     2
1 1 1 1       0     1     3
0 0 0 <DC>    0     2     1
1 0 1 <float> 1     2     2

In this example:

• Notice how the clock resets to 0 in each line that does a reset.
• The first two tests are combinational (seq=0), so the circuit resets between each test, even though they share set 0.
• The next three tests all have set 1 with seq values 1-3, so they form one sequence that runs in order without reset between each other only resetting before the first test in the set runs.
• The last test has set 2 seq 1&2, so it starts a new sequence and the circuit resets before it runs but not between tests in the set.
• The sixth test uses <DC> for the output, so any output value passes.
• The last test uses <float> for the output, expecting a floating value.

Thus the execution might look like this:

1. Reset, set A=0, B=0, C=0 and check that Out==0 and clk=0
2. Reset, set A=0, B=0, C=1 and check that Out==1 and clk=0
3. Reset, set A=1, B=1, C=0 and check that Out==1 and clk=0
4. Tick, set A=0, B=1, C=0 and check that Out==0 and clk=1
5. Tick, set A=1, B=1, C=1 and check that Out==1 and clk=0
6. Reset, set A=0, B=0, C=0 and not check Out but clk=0
7. Tick, set A=1, B=0, C=1 and check that Out is floating (in Logisim this is notated as U) and clk=1
8. Test Vector is complete

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