# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_RA6M5
	select ARM
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_MPU
	select CPU_HAS_RENESAS_RA_IDAU
	select HAS_RENESAS_RA_FSP
	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
	select CPU_CORTEX_M_HAS_DWT
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select FPU
	select HAS_SWO
	select XIP
	select GPIO_RA_HAS_VBTICTLR
	select OUTPUT_RPD if ETH_RENESAS_RA
	select SOC_RA_DYNAMIC_INTERRUPT_NUMBER

if SOC_SERIES_RA6M5

config RENESAS_PN_PACKAGE_TYPE
	int
	range 1 5
	default 4 if SOC_R7FA6M5BH3CFC
	help
	  Package type:
	  1 -> BG: FBGA 176 pins
	  2 -> BM: FBGA 144 pins
	  3 -> FB: LQFP 144 pins
	  4 -> FC: LQFP 176 pins
	  5 -> FP: LQFP 100 pins

config RENESAS_PN_FEATURE_SET
	hex
	default 0x42 if SOC_R7FA6M5BH3CFC
	help
	  Feature set (Convert the feature set character into its ASCII hex value):
	  - A (0x41): Supporting only Classical CAN (Not supporting Flexible Data rate)
	  - B (0x42): Supporting Classical CAN with Flexible Data rate

endif # SOC_SERIES_RA6M5
