 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_dedicated_network	  8.21	  vpr	  76.34 MiB	  	  0.09	  16896	  -1	  -1	  2	  0.10	  -1	  -1	  33580	  -1	  -1	  31	  311	  15	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  78172	  311	  156	  1019	  1160	  1	  965	  513	  28	  28	  784	  memory	  auto	  35.4 MiB	  0.52	  19372.9	  9596	  172881	  54219	  116791	  1871	  75.2 MiB	  0.63	  0.01	  5.23	  4.57747	  -3748.3	  -4.57747	  4.57747	  0.81	  0.00326476	  0.00272765	  0.277857	  0.240711	  -1	  -1	  -1	  -1	  40	  15592	  15	  4.25198e+07	  9.89071e+06	  2.15543e+06	  2749.27	  2.96	  1.00681	  0.892445	  78831	  435646	  -1	  14397	  13	  2630	  3073	  952101	  338016	  4.43552	  4.43552	  -4439.76	  -4.43552	  -356.757	  -1.26311	  2.69266e+06	  3434.52	  0.10	  0.74	  0.29	  -1	  -1	  0.10	  0.125657	  0.115392	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_dedicated_network	  7.85	  vpr	  76.85 MiB	  	  0.10	  16896	  -1	  -1	  2	  0.10	  -1	  -1	  33588	  -1	  -1	  31	  311	  15	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  78692	  311	  156	  1019	  1160	  1	  965	  513	  28	  28	  784	  memory	  auto	  35.0 MiB	  0.51	  19372.9	  9596	  172881	  54219	  116791	  1871	  75.7 MiB	  0.61	  0.01	  5.23	  4.57747	  -3748.3	  -4.57747	  4.57747	  0.77	  0.00321474	  0.00268382	  0.270278	  0.234188	  -1	  -1	  -1	  -1	  40	  15575	  12	  4.25198e+07	  9.89071e+06	  2.19000e+06	  2793.37	  2.78	  0.986447	  0.874865	  78831	  446382	  -1	  14613	  11	  2525	  2959	  723992	  214853	  4.80815	  4.80815	  -4793.38	  -4.80815	  -158.175	  -1.4614	  2.74289e+06	  3498.59	  0.11	  0.67	  0.30	  -1	  -1	  0.11	  0.114544	  0.105741	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_dedicated_network	  10.80	  vpr	  77.50 MiB	  	  0.10	  16896	  -1	  -1	  2	  0.10	  -1	  -1	  33580	  -1	  -1	  31	  311	  15	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  79364	  311	  156	  1019	  1160	  1	  965	  513	  28	  28	  784	  memory	  auto	  35.3 MiB	  0.51	  19372.9	  9466	  174933	  54791	  118050	  2092	  77.5 MiB	  0.60	  0.01	  5.23	  3.99998	  -3598.58	  -3.99998	  3.99998	  0.76	  0.00322229	  0.00269794	  0.267989	  0.230936	  -1	  -1	  -1	  -1	  36	  16714	  17	  4.25198e+07	  9.89071e+06	  1.96702e+06	  2508.96	  5.03	  1.15757	  1.02971	  76483	  392433	  -1	  15696	  13	  2724	  3126	  2352532	  1764808	  5.51612	  5.51612	  -4479.37	  -5.51612	  -1580.55	  -3.33136	  2.42368e+06	  3091.42	  0.09	  1.38	  0.26	  -1	  -1	  0.09	  0.126941	  0.117063	  15	  950	 
