arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
simple-7series.xml	stereovision3.v	common	1.50	vpr	63.36 MiB		-1	-1	0.20	32068	4	0.08	-1	-1	36436	-1	-1	14	10	0	-1	success	v8.0.0-14857-g1880999910-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-12-27T09:05:28	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	64880	10	2	181	183	1	68	26	7	7	49	clb	auto	23.9 MiB	0.52	309.154	251	1812	529	1154	129	63.4 MiB	0.02	0.00	2.51838	2.32583	-96.5416	-2.32583	2.32583	0.02	0.000162929	0.000148649	0.00892837	0.00816598	-1	-1	-1	-1	154	1672	11	0	0	294086.	6001.75	0.24	0.0163006	0.0148515	12242	48540	-1	1463	12	269	862	524384	291430	4.81596	4.81596	-165.257	-4.81596	-2.328	-0.04	377773.	7709.66	0.02	0.06	0.03	-1	-1	0.02	0.00660327	0.00604063	
