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# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
circuit_list_add=ch_intrinsics.v

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_standard.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements.timing_fail.txt

# Script parameters
script_params= --terminate_if_timing_fails on --max_router_iterations 150 
script_params_list_add= -sdc_file sdc/samples/impossible_pass_timing.sdc
