 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_frac_N10_mem32K_40nm.xml	  ch_intrinsics.v	  common	  2.25	  vpr	  70.50 MiB	  	  -1	  -1	  0.21	  29880	  3	  0.07	  -1	  -1	  36928	  -1	  -1	  68	  99	  1	  0	  success	  v8.0.0-15526-g305b62890a	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-09T20:00:05	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing	  72196	  99	  130	  344	  474	  1	  227	  298	  12	  12	  144	  clb	  auto	  30.9 MiB	  0.13	  1668.56	  690	  129648	  55098	  60714	  13836	  70.5 MiB	  0.30	  0.00	  2.39775	  1.86365	  -117.838	  -1.86365	  1.86365	  0.13	  0.000589643	  0.000520456	  0.0808905	  0.0712251	  -1	  -1	  -1	  -1	  44	  1336	  11	  5.66058e+06	  4.21279e+06	  360780.	  2505.42	  0.71	  0.238973	  0.212071	  13094	  71552	  -1	  1178	  8	  395	  637	  25786	  8224	  1.88517	  1.88517	  -135.497	  -1.88517	  -0.271099	  -0.0983812	  470765.	  3269.20	  0.02	  0.02	  0.06	  -1	  -1	  0.02	  0.0172656	  0.0159789	 
