arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_le	num_luts	num_add_blocks	max_add_chain_length	num_sub_blocks	max_sub_chain_length	
k6_frac_N10_tileable_4add_2chains_depop50_mem20K_22nm.xml	mult_4x4.v	common	0.84	vpr	65.54 MiB		-1	-1	0.05	26868	1	0.02	-1	-1	33584	-1	-1	3	9	0	-1	success	v8.0.0-14225-g4342c22cd	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-16T11:20:17	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	67116	9	8	75	70	1	34	20	5	5	25	clb	auto	26.7 MiB	0.28	116	90	1748	666	1058	24	65.5 MiB	0.01	0.00	2.64007	2.48207	-25.909	-2.48207	2.48207	0.01	4.9624e-05	4.3192e-05	0.0038928	0.00345585	-1	-1	-1	-1	50	161	10	151211	75605.7	65920.5	2636.82	0.09	0.0248261	0.0206066	2268	9878	-1	173	15	131	137	5446	2940	3.17075	3.17075	-36.7992	-3.17075	0	0	75291.5	3011.66	0.00	0.00	-1	-1	-1	0.00	0.00332879	0.00304368	13	18	-1	-1	-1	-1	
k6_frac_N10_tileable_4add_2chains_depop50_mem20K_22nm.xml	mult_5x5.v	common	1.47	vpr	66.29 MiB		-1	-1	0.05	27064	1	0.02	-1	-1	33616	-1	-1	2	11	0	-1	success	v8.0.0-14225-g4342c22cd	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-16T11:20:17	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	67876	11	10	108	97	1	48	23	4	4	16	clb	auto	26.9 MiB	0.95	145.745	128	2583	1037	1310	236	66.3 MiB	0.01	0.00	3.45122	3.45122	-42.3331	-3.45122	3.45122	0.00	6.7038e-05	5.9624e-05	0.00632755	0.00569176	-1	-1	-1	-1	34	249	43	50403.8	50403.8	23426.9	1464.18	0.05	0.0239533	0.0203792	1028	3252	-1	160	22	166	204	5202	3250	3.63893	3.63893	-49.1362	-3.63893	0	0	27734.3	1733.39	0.00	0.01	-1	-1	-1	0.00	0.00506793	0.00455842	14	27	-1	-1	-1	-1	
k6_frac_N10_tileable_4add_2chains_depop50_mem20K_22nm.xml	mult_6x6.v	common	2.60	vpr	66.59 MiB		-1	-1	0.06	26996	1	0.02	-1	-1	33612	-1	-1	7	13	0	-1	success	v8.0.0-14225-g4342c22cd	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-16T11:20:17	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	68184	13	12	149	129	1	68	32	6	6	36	clb	auto	27.1 MiB	1.89	259.236	212	4632	1940	2581	111	66.6 MiB	0.02	0.00	3.49758	3.33958	-50.3198	-3.33958	3.33958	0.02	9.964e-05	8.9661e-05	0.0099402	0.00892025	-1	-1	-1	-1	50	448	24	403230	176413	114219.	3172.75	0.17	0.0522518	0.0440853	4042	17995	-1	405	19	331	424	16811	8229	4.43798	4.43798	-68.6911	-4.43798	0	0	129542.	3598.40	0.00	0.01	-1	-1	-1	0.00	0.0061218	0.00554889	25	38	-1	-1	-1	-1	
k6_frac_N10_tileable_4add_2chains_depop50_mem20K_22nm.xml	mult_7x7.v	common	1.63	vpr	67.05 MiB		-1	-1	0.04	27060	1	0.02	-1	-1	33804	-1	-1	7	15	0	-1	success	v8.0.0-14225-g4342c22cd	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-16T11:20:17	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	68664	15	14	196	165	1	92	36	6	6	36	clb	auto	27.3 MiB	0.92	339.362	304	2396	623	1729	44	67.1 MiB	0.01	0.00	3.5903	3.5903	-63.6508	-3.5903	3.5903	0.02	0.000121131	0.000108627	0.0062971	0.00575398	-1	-1	-1	-1	42	828	45	403230	176413	92384.0	2566.22	0.20	0.0560352	0.0474895	3864	15929	-1	560	20	579	851	25757	12596	5.07201	5.07201	-89.3028	-5.07201	0	0	117700.	3269.43	0.00	0.01	-1	-1	-1	0.00	0.00787118	0.00713626	37	51	-1	-1	-1	-1	
k6_frac_N10_tileable_4add_2chains_depop50_mem20K_22nm.xml	mult_8x8.v	common	3.09	vpr	67.23 MiB		-1	-1	0.05	27256	1	0.02	-1	-1	34100	-1	-1	5	17	0	-1	success	v8.0.0-14225-g4342c22cd	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-16T11:20:17	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	68844	17	16	251	206	1	117	38	5	5	25	clb	auto	27.5 MiB	2.47	488.93	398	6338	2983	3309	46	67.2 MiB	0.03	0.00	3.81172	3.75891	-72.5304	-3.75891	3.75891	0.01	0.000150076	0.000135558	0.0167927	0.0151883	-1	-1	-1	-1	50	603	23	151211	126010	65920.5	2636.82	0.09	0.050922	0.0442358	2268	9878	-1	566	18	616	953	26361	12557	4.46876	4.46876	-90.4923	-4.46876	0	0	75291.5	3011.66	0.00	0.01	-1	-1	-1	0.00	0.00926488	0.00846032	44	66	-1	-1	-1	-1	
k6_frac_N10_tileable_4add_2chains_depop50_mem20K_22nm.xml	mult_9x9.v	common	2.97	vpr	67.07 MiB		-1	-1	0.06	26868	1	0.03	-1	-1	34100	-1	-1	7	19	0	-1	success	v8.0.0-14225-g4342c22cd	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-16T11:20:17	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	68684	19	18	308	249	1	134	44	6	6	36	clb	auto	27.5 MiB	2.25	669.263	452	6743	3279	3431	33	67.1 MiB	0.03	0.00	4.665	4.6966	-95.9059	-4.6966	4.6966	0.02	0.000181766	0.000163711	0.0179309	0.0161721	-1	-1	-1	-1	50	992	37	403230	176413	114219.	3172.75	0.14	0.0624032	0.0540746	4042	17995	-1	770	19	731	1213	38440	18356	6.13013	6.13013	-126.291	-6.13013	0	0	129542.	3598.40	0.00	0.02	-1	-1	-1	0.00	0.01127	0.0102749	53	83	-1	-1	-1	-1	
