#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
# circuit_list_add=arm_core.v
circuit_list_add=boundtop_nolatches.v
circuit_list_add=ch_intrinsics_nolatches.v
circuit_list_add=diffeq1.v
circuit_list_add=diffeq2.v
# circuit_list_add=or1200.v
circuit_list_add=raygentop_nolatches.v
circuit_list_add=stereovision3.v

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_fixed_chan_width.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

#Script parameters
script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang --route_chan_width 128

