##############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/

# Path to directory of architectures to use
archs_dir=arch/

# Add circuits to list to sweep
circuit_list_add=verilog/multiclock_output_and_latch.v
circuit_list_add=verilog/and_latch.v

# Add architectures to list to sweep
arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml
arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml
arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml

# Parse info and how to parse
parse_file=vpr_clock_modeling.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
# A pass requirement to check that the number of routed nets
# are equal can change if the circuit is synthesized
# differently. At that point a new golden results file must
# be created and checked to see that using the route option
# increases the number of routed nets.
pass_requirements_file=pass_requirements_clock_modeling.txt

# Script parameters
# Since the used benchmarks in this test are small, a small target_utilization has been set to that the created grid is large enough for the clock network to get built properly 
script_params_list_add= --target_utilization 0.01 --two_stage_clock_routing -read_vpr_constraints tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml --clock_modeling dedicated_network
