arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
stratixiv_arch.timing.xml	styr.blif	common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar	23.59	vpr	981.03 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1004572	10	10	168	178	1	65	30	11	8	88	io	auto	955.2 MiB	0.42	461.816	356	858	83	757	18	981.0 MiB	0.07	0.00	6.74915	6.51193	-68.9608	-6.51193	6.51193	1.27	0.000334488	0.000301626	0.0103413	0.0096093	-1	-1	-1	-1	20	918	34	0	0	100248.	1139.18	0.83	0.124998	0.109388	11180	23751	-1	845	23	476	1650	114111	57511	6.78383	6.78383	-76.9391	-6.78383	0	0	125464.	1425.72	0.00	0.07	0.03	-1	-1	0.00	0.0224221	0.0204538	
stratixiv_arch.timing.xml	styr.blif	common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar	24.51	vpr	979.80 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1003320	10	10	168	178	1	65	30	11	8	88	io	auto	954.4 MiB	0.41	461.816	359	766	56	697	13	979.8 MiB	0.07	0.00	6.74915	6.50519	-69.5857	-6.50519	6.50519	1.20	0.000302625	0.000275588	0.00840489	0.00786073	-1	-1	-1	-1	20	821	20	0	0	100248.	1139.18	0.82	0.107907	0.0942646	11180	23751	-1	702	14	347	1251	69013	37376	6.89984	6.89984	-75.6571	-6.89984	0	0	125464.	1425.72	0.00	0.06	0.03	-1	-1	0.00	0.0181492	0.0168752	
stratixiv_arch.timing.xml	styr.blif	common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra	24.46	vpr	980.39 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1003924	10	10	168	178	1	65	30	11	8	88	io	auto	954.5 MiB	0.40	461.816	374	812	74	723	15	980.4 MiB	0.07	0.00	6.74915	6.37842	-69.1049	-6.37842	6.37842	1.74	0.000304257	0.000278588	0.009051	0.00841697	-1	-1	-1	-1	20	875	24	0	0	100248.	1139.18	0.77	0.099881	0.0870212	11180	23751	-1	836	16	452	1751	105753	53661	7.04259	7.04259	-77.5055	-7.04259	0	0	125464.	1425.72	0.00	0.07	0.03	-1	-1	0.00	0.0215184	0.0198249	
stratixiv_arch.timing.xml	styr.blif	common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra	24.63	vpr	980.21 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1003740	10	10	168	178	1	65	30	11	8	88	io	auto	954.1 MiB	0.40	461.816	355	766	61	687	18	980.2 MiB	0.07	0.00	6.74915	6.37842	-69.2216	-6.37842	6.37842	1.77	0.000305069	0.000278111	0.00850764	0.00795101	-1	-1	-1	-1	18	981	33	0	0	88979.3	1011.13	0.35	0.0620621	0.0547876	11100	22242	-1	762	17	414	1573	93563	46602	6.85135	6.85135	-77.7111	-6.85135	0	0	114778.	1304.29	0.00	0.06	0.03	-1	-1	0.00	0.0201433	0.0185545	
