 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k4_n4_v7_bidir.xml	  styr.blif	  common	  1.37	  vpr	  62.60 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  72	  10	  -1	  -1	  success	  b2bdea1	  Release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64	  2025-06-18T23:25:54	  pkrvmxyh4eaekms	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  64104	  10	  10	  253	  263	  1	  171	  92	  11	  11	  121	  clb	  auto	  23.5 MiB	  0.04	  1829.24	  1329	  4646	  728	  3820	  98	  62.6 MiB	  0.05	  0.00	  8.75156	  5.65828	  -74.3763	  -5.65828	  5.65828	  0.08	  0.000539066	  0.000438929	  0.0158895	  0.0133045	  -1	  -1	  -1	  -1	  14	  1972	  27	  2.43e+06	  2.16e+06	  -1	  -1	  0.65	  0.146019	  0.12287	  3402	  27531	  -1	  1970	  16	  1168	  4226	  219209	  27455	  7.33108	  7.33108	  -92.5065	  -7.33108	  0	  0	  -1	  -1	  0.01	  0.07	  0.02	  -1	  -1	  0.01	  0.0241699	  0.0213263	 
 k4_n4_v7_longline_bidir.xml	  styr.blif	  common	  1.77	  vpr	  63.19 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  72	  10	  -1	  -1	  success	  b2bdea1	  Release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64	  2025-06-18T23:25:54	  pkrvmxyh4eaekms	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  64704	  10	  10	  253	  263	  1	  171	  92	  11	  11	  121	  clb	  auto	  23.6 MiB	  0.04	  1829.24	  1305	  3404	  389	  2964	  51	  63.2 MiB	  0.04	  0.00	  5.19817	  4.46893	  -53.8773	  -4.46893	  4.46893	  0.09	  0.000510361	  0.000414222	  0.0114433	  0.00959255	  -1	  -1	  -1	  -1	  18	  2312	  35	  2.43e+06	  2.16e+06	  -1	  -1	  1.02	  0.19335	  0.161505	  3282	  34431	  -1	  2326	  21	  1300	  4425	  297597	  37882	  9.34193	  9.34193	  -107.688	  -9.34193	  0	  0	  -1	  -1	  0.02	  0.09	  0.03	  -1	  -1	  0.02	  0.0293867	  0.0256624	 
 k4_n4_v7_l1_bidir.xml	  styr.blif	  common	  1.82	  vpr	  62.58 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  72	  10	  -1	  -1	  success	  b2bdea1	  Release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64	  2025-06-18T23:25:54	  pkrvmxyh4eaekms	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  64084	  10	  10	  253	  263	  1	  171	  92	  11	  11	  121	  clb	  auto	  23.7 MiB	  0.04	  1829.24	  1283	  8993	  1996	  6843	  154	  62.6 MiB	  0.10	  0.00	  11.3865	  6.82489	  -85.7025	  -6.82489	  6.82489	  0.10	  0.000535759	  0.000437145	  0.0267342	  0.0222548	  -1	  -1	  -1	  -1	  10	  1437	  37	  2.43e+06	  2.16e+06	  -1	  -1	  0.95	  0.1205	  0.101293	  4482	  22551	  -1	  1348	  24	  1290	  4977	  336418	  74151	  8.81482	  8.81482	  -100.507	  -8.81482	  0	  0	  -1	  -1	  0.01	  0.12	  0.02	  -1	  -1	  0.01	  0.0332838	  0.0290833	 
 k4_n4_v7_bidir_pass_gate.xml	  styr.blif	  common	  2.05	  vpr	  63.22 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  72	  10	  -1	  -1	  success	  b2bdea1	  Release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64	  2025-06-18T23:25:54	  pkrvmxyh4eaekms	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  64736	  10	  10	  253	  263	  1	  171	  92	  11	  11	  121	  clb	  auto	  23.6 MiB	  0.04	  1829.24	  1294	  4025	  499	  3414	  112	  63.2 MiB	  0.05	  0.00	  4.50889	  3.4607	  -44.4554	  -3.4607	  3.4607	  0.09	  0.00054143	  0.000441935	  0.0136548	  0.0114763	  -1	  -1	  -1	  -1	  16	  2079	  28	  2.43e+06	  2.16e+06	  -1	  -1	  1.10	  0.148452	  0.124941	  3522	  30407	  -1	  2152	  25	  1482	  5545	  978183	  174036	  26.5946	  26.5946	  -260	  -26.5946	  0	  0	  -1	  -1	  0.01	  0.28	  0.03	  -1	  -1	  0.01	  0.0329671	  0.0287146	 
