 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 fixed_k6_frac_N8_22nm.xml	  single_wire.v	  common	  1.18	  vpr	  82.25 MiB	  	  -1	  -1	  0.07	  27696	  1	  0.02	  -1	  -1	  32920	  -1	  -1	  0	  1	  0	  0	  success	  v8.0.0-15501-g59ac66b815-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-05T14:33:22	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing	  84228	  1	  1	  1	  2	  0	  1	  2	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  2	  2	  3	  0	  3	  0	  82.3 MiB	  0.68	  0.00	  0.271506	  0.271506	  -0.271506	  -0.271506	  nan	  0.00	  8.791e-06	  5.671e-06	  6.1395e-05	  4.3072e-05	  82.3 MiB	  0.68	  82.3 MiB	  0.05	  8	  4	  1	  6.79088e+06	  0	  166176.	  575.005	  0.14	  0.000810261	  0.000735033	  20206	  45088	  -1	  4	  1	  1	  1	  21	  11	  0.2714	  nan	  -0.2714	  -0.2714	  0	  0	  202963.	  702.294	  0.01	  0.00	  0.04	  -1	  -1	  0.01	  0.000766876	  0.000705779	 
