##############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing/fixed_size

# TODO: Add a path to the atom constraints (different from the place constraints)
# "atom_const_dir"
# TODO: Add a directory next to the config to hold the constraints.

# Add circuits to list to sweep
circuit_list_add=single_wire.v
circuit_list_add=single_ff.v
circuit_list_add=ch_intrinsics.v
circuit_list_add=diffeq1.v

# Add architectures to list to sweep
arch_list_add=fixed_k6_frac_N8_22nm.xml

# Constrain the circuits to a fixed device with fixed IO constraints.
circuit_constraint_list_add=(single_wire.v, arch=fixed_k6_frac_N8_22nm.xml)
circuit_constraint_list_add=(single_wire.v, device=unnamed_device)
circuit_constraint_list_add=(single_wire.v, constraints=../../../../constraints/single_wire_fixed_io.xml)

circuit_constraint_list_add=(single_ff.v, arch=fixed_k6_frac_N8_22nm.xml)
circuit_constraint_list_add=(single_ff.v, device=unnamed_device)
circuit_constraint_list_add=(single_ff.v, constraints=../../../../constraints/single_ff_fixed_io.xml)

circuit_constraint_list_add=(ch_intrinsics.v, arch=fixed_k6_frac_N8_22nm.xml)
circuit_constraint_list_add=(ch_intrinsics.v, device=unnamed_device)
circuit_constraint_list_add=(ch_intrinsics.v, constraints=../../../../constraints/ch_intrinsics_fixed_io.xml)

circuit_constraint_list_add=(diffeq1.v, arch=fixed_k6_frac_N8_22nm.xml)
circuit_constraint_list_add=(diffeq1.v, device=unnamed_device)
circuit_constraint_list_add=(diffeq1.v, constraints=../../../../constraints/diffeq1_fixed_io.xml)

# Parse info and how to parse
parse_file=vpr_standard.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements_ap.txt

# Script parameters
script_params_common=-track_memory_usage --analytical_place --route

