#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog/koios

# Path to directory of architectures to use
archs_dir=arch/COFFE_22nm

# Add circuits to list to sweep
# Some of these benchmarks are designs with hard dsp and ram blocks.
# But in this task, we're running them without enabling these
# blocks (that is, the macros `complex_dsp` and `hard_mem` area not defined).
circuit_list_add=bwave_like.float.small.v
#Commenting out the following because of https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2149
#circuit_list_add=bwave_like.fixed.large.v
circuit_list_add=dnnweaver.v
circuit_list_add=tdarknet_like.small.v

# Add architectures to list to sweep
arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

#Script parameters
script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300
