############################################
# Configuration file for running experiments
##############################################

# Path to directory of architectures to use
archs_dir=arch/xilinx

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Add architectures to list
arch_list_add=7series_BRAM_DSP_carry.xml

# Add circuits to list to sweep
circuit_list_add=mcml.v
circuit_list_add=LU32PEEng.v
circuit_list_add=LU8PEEng.v
circuit_list_add=bgm.v
circuit_list_add=stereovision0.v
circuit_list_add=stereovision1.v
circuit_list_add=stereovision2.v

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_vpr_xilinx.txt

# Pass requirements
pass_requirements_file=pass_requirements_vpr_xilinx_fixed_width.txt

# Xilinx Benchmarks route at the physical channel 
# width of the chip which is 190. Flat routing is
# also enabled.
script_params=--route_chan_width 190 --flat_routing on