arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	
k4_N10_memSize16384_memData64.xml	ch_intrinsics_modified.v	common	1.11	vpr	62.57 MiB		-1	-1	0.21	18340	3	0.06	-1	-1	32272	-1	-1	72	99	1	0	success	v8.0.0-12648-g259ceba57-dirty	release IPO VTR_ASSERT_LEVEL=2	Clang 18.1.3 on Linux-6.8.0-58-generic x86_64	2025-05-06T12:34:13	betzgrp-wintermute	/home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks	64072	99	130	353	483	1	221	302	13	13	169	clb	auto	22.8 MiB	0.03	1823	708	26614	3324	9855	13435	62.6 MiB	0.02	0.00	28	1654	13	3.33e+06	2.28e+06	384474.	2275.00	0.12	
