#
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# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog

# Path to directory of architectures to use
archs_dir=arch/timing/fraclut_carrychain

# Add circuits to list to sweep
#Issue 1369 (circuit does not go through odin) 
circuit_list_add=64-16bit-fixed-JACM.v

# Add architectures to list to sweep
arch_list_add=k6_frac_2ripple_N8_22nm.xml
arch_list_add=k6_frac_2uripple_N8_22nm.xml
arch_list_add=k6_frac_N8_22nm.xml
arch_list_add=k6_frac_ripple_N8_22nm.xml
arch_list_add=k6_frac_uripple_N8_22nm.xml

# Parse info and how to parse
parse_file=vpr_chain.txt

# Pass requirements
pass_requirements_file=pass_requirements_chain.txt

script_params=-lut_size 6 -routing_failure_predictor off
