 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	 
 k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml	  ch_intrinsics.v	  common	  5.28	  vpr	  65.87 MiB	  	  0.06	  9504	  -1	  -1	  3	  0.30	  -1	  -1	  34508	  -1	  -1	  69	  99	  1	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  67448	  99	  130	  363	  493	  1	  251	  299	  13	  13	  169	  clb	  auto	  26.3 MiB	  0.79	  804	  78221	  18305	  27577	  32339	  65.9 MiB	  0.15	  0.00	  30	  1517	  12	  0	  0	  423577.	  2506.37	  2.58	 
