 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_N10_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	  0.41	  vpr	  57.28 MiB	  	  0.00	  6388	  -1	  -1	  1	  0.03	  -1	  -1	  29960	  -1	  -1	  1	  2	  -1	  -1	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  58652	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  18.6 MiB	  0.00	  6	  9	  3	  5	  1	  57.3 MiB	  0.04	  0.00	  0.55447	  -0.91031	  -0.55447	  0.55447	  0.00	  2.1796e-05	  1.6522e-05	  0.000193754	  0.00015861	  -1	  -1	  -1	  -1	  -1	  2	  4	  18000	  18000	  14049.7	  1561.07	  0.00	  0.00168667	  0.00157156	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	 
 timing/k6_N10_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_-start_odin_--clock_modeling_route_--route_chan_width_60	  0.39	  vpr	  57.19 MiB	  	  0.00	  6340	  -1	  -1	  1	  0.03	  -1	  -1	  29884	  -1	  -1	  1	  2	  -1	  -1	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  58560	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  18.5 MiB	  0.00	  9	  9	  3	  3	  3	  57.2 MiB	  0.00	  0.00	  0.48631	  -0.91031	  -0.48631	  0.48631	  0.00	  1.7329e-05	  1.1723e-05	  0.000120696	  9.1803e-05	  -1	  -1	  -1	  -1	  -1	  4	  3	  18000	  18000	  15707.9	  1745.32	  0.00	  0.00149934	  0.00140654	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0	  3	 
 timing/k6_N10_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	  5.17	  vpr	  59.21 MiB	  	  0.36	  59164	  -1	  -1	  2	  1.59	  -1	  -1	  50532	  -1	  -1	  155	  5	  -1	  -1	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  60628	  5	  156	  191	  347	  1	  163	  316	  15	  15	  225	  clb	  auto	  19.6 MiB	  0.04	  29	  84166	  60542	  3208	  20416	  59.2 MiB	  0.13	  0.00	  1.49664	  -15.1312	  -1.49664	  1.49664	  0.00	  0.000406843	  0.000383604	  0.0325033	  0.0306122	  -1	  -1	  -1	  -1	  -1	  40	  7	  3.042e+06	  2.79e+06	  863192.	  3836.41	  0.01	  0.0416902	  0.0390742	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  154	  9	 
 timing/k6_N10_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_route_--route_chan_width_60	  5.29	  vpr	  59.23 MiB	  	  0.44	  59264	  -1	  -1	  2	  1.66	  -1	  -1	  50664	  -1	  -1	  155	  5	  -1	  -1	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  60656	  5	  156	  191	  347	  1	  163	  316	  15	  15	  225	  clb	  auto	  19.6 MiB	  0.04	  36	  74491	  53339	  3165	  17987	  59.2 MiB	  0.11	  0.00	  1.49775	  -14.6149	  -1.49775	  1.49775	  0.00	  0.000376659	  0.000354057	  0.027722	  0.0260055	  -1	  -1	  -1	  -1	  -1	  54	  6	  3.042e+06	  2.79e+06	  892591.	  3967.07	  0.01	  0.0361212	  0.0337603	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  153	  10	 
 timing/k6_N10_mem32K_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	  0.34	  vpr	  62.88 MiB	  	  0.01	  6524	  -1	  -1	  1	  0.03	  -1	  -1	  30032	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  64384	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  24.1 MiB	  0.00	  6	  9	  3	  5	  1	  62.9 MiB	  0.00	  0.00	  0.55247	  -0.90831	  -0.55247	  0.55247	  0.00	  1.8462e-05	  1.3116e-05	  0.000143184	  0.000107932	  -1	  -1	  -1	  -1	  -1	  2	  3	  53894	  53894	  12370.0	  1374.45	  0.00	  0.00154548	  0.00142994	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	 
 timing/k6_N10_mem32K_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_-start_odin_--clock_modeling_route_--route_chan_width_60	  0.38	  vpr	  62.88 MiB	  	  0.01	  6520	  -1	  -1	  1	  0.02	  -1	  -1	  29980	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  64388	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  24.1 MiB	  0.00	  9	  9	  3	  3	  3	  62.9 MiB	  0.00	  0.00	  0.48631	  -0.90831	  -0.48631	  0.48631	  0.00	  1.7389e-05	  1.2439e-05	  0.000110474	  8.1262e-05	  -1	  -1	  -1	  -1	  -1	  4	  2	  53894	  53894	  14028.3	  1558.70	  0.00	  0.00162603	  0.00153736	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0	  3	 
 timing/k6_N10_mem32K_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	  4.85	  vpr	  69.68 MiB	  	  0.15	  16496	  -1	  -1	  2	  0.15	  -1	  -1	  33692	  -1	  -1	  43	  311	  15	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  71352	  311	  156	  972	  1128	  1	  953	  525	  28	  28	  784	  memory	  auto	  30.0 MiB	  0.53	  9455	  210108	  77830	  122308	  9970	  69.7 MiB	  1.15	  0.02	  3.97422	  -4336.45	  -3.97422	  3.97422	  0.00	  0.00487926	  0.00437885	  0.503553	  0.447369	  -1	  -1	  -1	  -1	  -1	  13425	  12	  4.25198e+07	  1.05374e+07	  2.96205e+06	  3778.13	  0.40	  0.699755	  0.628908	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  15	  938	 
 timing/k6_N10_mem32K_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_route_--route_chan_width_60	  5.65	  vpr	  69.53 MiB	  	  0.19	  16512	  -1	  -1	  2	  0.16	  -1	  -1	  33768	  -1	  -1	  43	  311	  15	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  71200	  311	  156	  972	  1128	  1	  953	  525	  28	  28	  784	  memory	  auto	  29.9 MiB	  0.55	  9870	  203757	  68308	  124561	  10888	  69.5 MiB	  1.17	  0.02	  3.91483	  -3854.15	  -3.91483	  3.91483	  0.00	  0.00501054	  0.00442487	  0.50283	  0.44465	  -1	  -1	  -1	  -1	  -1	  13822	  12	  4.25198e+07	  1.05374e+07	  3.02951e+06	  3864.17	  0.47	  0.720818	  0.646017	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  14	  939	 
