 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	  verilog/multiclock_output_and_latch.v	  common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	  2.16	  vpr	  63.70 MiB	  	  -1	  -1	  0.16	  17284	  1	  0.06	  -1	  -1	  32000	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  65232	  6	  1	  16	  17	  2	  10	  9	  17	  17	  289	  -1	  auto	  25.0 MiB	  0.02	  30	  162	  45	  109	  8	  63.7 MiB	  0.00	  0.00	  1.4327	  -4.13089	  -1.4327	  0.805	  0.31	  4.4099e-05	  3.5968e-05	  0.000975677	  0.000805323	  -1	  -1	  -1	  -1	  20	  95	  2	  1.34605e+07	  107788	  411619.	  1424.29	  0.26	  0.0027188	  0.00241641	  24098	  82050	  -1	  103	  2	  14	  14	  8039	  3790	  2.67718	  0.805	  -5.78255	  -2.67718	  -1.39285	  -0.696976	  535376.	  1852.51	  0.02	  0.11	  0.08	  -1	  -1	  0.02	  0.00161741	  0.0015267	  1	  9	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	  verilog/and_latch.v	  common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	  1.43	  vpr	  63.80 MiB	  	  -1	  -1	  0.14	  17204	  1	  0.02	  -1	  -1	  29892	  -1	  -1	  1	  3	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  65328	  3	  1	  5	  6	  1	  4	  5	  13	  13	  169	  -1	  auto	  25.1 MiB	  0.01	  35	  12	  3	  8	  1	  63.8 MiB	  0.00	  0.00	  1.12186	  -1.54831	  -1.12186	  1.12186	  0.17	  1.9668e-05	  1.555e-05	  0.000140847	  0.000116689	  -1	  -1	  -1	  -1	  20	  62	  1	  6.63067e+06	  53894	  227243.	  1344.63	  0.15	  0.00174765	  0.00164276	  13251	  44387	  -1	  55	  1	  4	  4	  2056	  1112	  1.77078	  1.77078	  -1.77078	  -1.77078	  -0.365681	  -0.365681	  294987.	  1745.49	  0.01	  0.06	  0.04	  -1	  -1	  0.01	  0.00118856	  0.00114905	  0	  4	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	  verilog/multiclock_output_and_latch.v	  common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	  2.17	  vpr	  63.78 MiB	  	  -1	  -1	  0.15	  17104	  1	  0.06	  -1	  -1	  32096	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  65312	  6	  1	  16	  17	  2	  10	  9	  17	  17	  289	  -1	  auto	  25.1 MiB	  0.02	  30	  162	  45	  109	  8	  63.8 MiB	  0.00	  0.00	  1.43377	  -4.13192	  -1.43377	  0.805	  0.31	  4.4431e-05	  3.6524e-05	  0.000996748	  0.000831767	  -1	  -1	  -1	  -1	  20	  96	  2	  1.34605e+07	  107788	  424167.	  1467.71	  0.26	  0.00281601	  0.00251628	  24098	  84646	  -1	  93	  2	  14	  14	  7618	  3614	  2.36211	  0.805	  -5.14799	  -2.36211	  -1.39063	  -0.695869	  547923.	  1895.93	  0.02	  0.12	  0.08	  -1	  -1	  0.02	  0.00158732	  0.00149878	  1	  9	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	  verilog/and_latch.v	  common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	  1.42	  vpr	  63.84 MiB	  	  -1	  -1	  0.15	  17300	  1	  0.02	  -1	  -1	  29808	  -1	  -1	  1	  3	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  65372	  3	  1	  5	  6	  1	  4	  5	  13	  13	  169	  -1	  auto	  25.1 MiB	  0.01	  35	  12	  3	  8	  1	  63.8 MiB	  0.00	  0.00	  1.12186	  -1.54831	  -1.12186	  1.12186	  0.18	  2.4637e-05	  1.8571e-05	  0.000161099	  0.000130017	  -1	  -1	  -1	  -1	  20	  58	  1	  6.63067e+06	  53894	  235789.	  1395.20	  0.16	  0.00138134	  0.00127269	  13251	  46155	  -1	  59	  1	  4	  4	  2248	  1144	  1.92085	  1.92085	  -1.92085	  -1.92085	  -0.365681	  -0.365681	  303533.	  1796.05	  0.01	  0.06	  0.04	  -1	  -1	  0.01	  0.00119868	  0.0011619	  0	  4	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	  verilog/multiclock_output_and_latch.v	  common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	  2.13	  vpr	  63.73 MiB	  	  -1	  -1	  0.11	  17264	  1	  0.06	  -1	  -1	  31968	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  65264	  6	  1	  16	  17	  2	  10	  9	  17	  17	  289	  -1	  auto	  25.1 MiB	  0.02	  30	  162	  45	  109	  8	  63.7 MiB	  0.00	  0.00	  1.4327	  -4.13089	  -1.4327	  0.805	  0.31	  4.4509e-05	  3.6501e-05	  0.000996459	  0.000829396	  -1	  -1	  -1	  -1	  20	  573	  2	  1.34605e+07	  107788	  408865.	  1414.76	  0.27	  0.00271534	  0.00241633	  24098	  82150	  -1	  581	  2	  13	  13	  6290	  3261	  3.57936	  0.805	  -7.58692	  -3.57936	  -3.19721	  -1.59916	  532630.	  1843.01	  0.02	  0.11	  0.08	  -1	  -1	  0.02	  0.00156771	  0.00147897	  1	  9	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	  verilog/and_latch.v	  common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	  1.38	  vpr	  64.10 MiB	  	  -1	  -1	  0.09	  17324	  1	  0.02	  -1	  -1	  29888	  -1	  -1	  1	  3	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  65636	  3	  1	  5	  6	  1	  4	  5	  13	  13	  169	  -1	  auto	  25.4 MiB	  0.01	  35	  12	  3	  8	  1	  64.1 MiB	  0.00	  0.00	  1.12186	  -1.54831	  -1.12186	  1.12186	  0.17	  1.8984e-05	  1.5001e-05	  0.000130743	  0.000106565	  -1	  -1	  -1	  -1	  20	  193	  1	  6.63067e+06	  53894	  225153.	  1332.26	  0.15	  0.00137629	  0.00128301	  13251	  44463	  -1	  186	  1	  4	  4	  914	  327	  2.39001	  2.39001	  -2.39001	  -2.39001	  -0.984912	  -0.984912	  292904.	  1733.16	  0.01	  0.06	  0.04	  -1	  -1	  0.01	  0.00119643	  0.00115763	  0	  4	 
