 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	  0.36	  vpr	  57.06 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  58432	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  18.1 MiB	  0.01	  21	  27	  11	  8	  8	  57.1 MiB	  0.00	  0.00	  2.44626	  0	  0	  2.44626	  0.01	  8.4124e-05	  7.6141e-05	  0.000566872	  0.000521479	  -1	  -1	  -1	  -1	  8	  13	  5	  72000	  72000	  5593.62	  349.601	  0.03	  0.00897084	  0.00748051	  672	  1128	  -1	  13	  6	  23	  23	  467	  160	  2.38826	  2.38826	  0	  0	  0	  0	  6492.02	  405.751	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00246625	  0.00224096	 
 timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	  0.36	  vpr	  57.18 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  58548	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  18.1 MiB	  0.01	  21	  27	  11	  8	  8	  57.2 MiB	  0.00	  0.00	  2.44626	  0	  0	  2.44626	  0.01	  8.4091e-05	  7.6218e-05	  0.000533212	  0.000493893	  -1	  -1	  -1	  -1	  8	  13	  5	  72000	  72000	  5593.62	  349.601	  0.03	  0.00878674	  0.00728191	  672	  1128	  -1	  13	  6	  23	  23	  467	  160	  2.38826	  2.38826	  0	  0	  0	  0	  6492.02	  405.751	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00243075	  0.00220629	 
 timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	  0.35	  vpr	  57.11 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  58476	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  18.2 MiB	  0.01	  21	  27	  11	  8	  8	  57.1 MiB	  0.00	  0.00	  2.44626	  0	  0	  2.44626	  0.01	  7.2279e-05	  6.4063e-05	  0.000526626	  0.000486058	  -1	  -1	  -1	  -1	  8	  13	  5	  72000	  72000	  5593.62	  349.601	  0.03	  0.00880952	  0.00732563	  672	  1128	  -1	  13	  6	  23	  23	  467	  160	  2.38826	  2.38826	  0	  0	  0	  0	  6492.02	  405.751	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00247494	  0.00224754	 
