 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	  2.08	  vpr	  61.77 MiB	  	  -1	  -1	  0.12	  16500	  1	  0.10	  -1	  -1	  31836	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  63252	  6	  1	  13	  14	  2	  8	  9	  4	  4	  16	  clb	  auto	  23.2 MiB	  0.01	  22	  27	  6	  15	  6	  61.8 MiB	  0.00	  0.00	  1.02737	  -3.61973	  -1.02737	  0.545	  0.01	  3.6498e-05	  2.6643e-05	  0.000260655	  0.000218319	  -1	  -1	  -1	  -1	  20	  22	  8	  107788	  107788	  10441.3	  652.579	  0.01	  0.00250948	  0.00220504	  742	  1670	  -1	  21	  1	  6	  6	  146	  96	  1.40641	  0.545	  -4.38899	  -1.40641	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00176399	  0.00169239	 
 k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	  2.09	  vpr	  61.68 MiB	  	  -1	  -1	  0.15	  16776	  1	  0.07	  -1	  -1	  31648	  -1	  -1	  2	  3	  0	  0	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  63160	  3	  -1	  23	  23	  2	  3	  5	  4	  4	  16	  clb	  auto	  23.2 MiB	  0.01	  3	  12	  2	  3	  7	  61.7 MiB	  0.00	  0.00	  0.620297	  -7.93119	  -0.620297	  0.545	  0.01	  6.5504e-05	  5.6164e-05	  0.000543565	  0.00049453	  -1	  -1	  -1	  -1	  8	  1	  1	  107788	  107788	  4888.88	  305.555	  0.01	  0.00311117	  0.00290556	  622	  902	  -1	  1	  1	  1	  1	  8	  6	  0.54641	  0.545	  -7.63564	  -0.54641	  0	  0	  5552.67	  347.042	  0.00	  0.01	  0.00	  -1	  -1	  0.00	  0.00221081	  0.00210995	 
 k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	  2.05	  vpr	  61.70 MiB	  	  -1	  -1	  0.10	  16420	  1	  0.10	  -1	  -1	  30004	  -1	  -1	  1	  3	  0	  0	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  63180	  3	  1	  5	  6	  1	  4	  5	  3	  3	  9	  -1	  auto	  23.1 MiB	  0.01	  9	  12	  5	  4	  3	  61.7 MiB	  0.00	  0.00	  0.52647	  -0.88231	  -0.52647	  0.52647	  0.00	  2.1504e-05	  1.601e-05	  0.000159881	  0.000125763	  -1	  -1	  -1	  -1	  20	  10	  1	  53894	  53894	  4880.82	  542.314	  0.01	  0.00174411	  0.00161402	  379	  725	  -1	  22	  1	  3	  3	  79	  69	  1.8363	  1.8363	  -2.38182	  -1.8363	  0	  0	  6579.40	  731.044	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00154197	  0.00149823	 
