arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	
k4_N10_memSize16384_memData64.xml	ch_intrinsics_modified.v	common	2.61	vpr	62.39 MiB		0.07	9224	-1	-1	4	0.25	-1	-1	34556	-1	-1	78	99	1	0	success	v8.0.0-11852-g026644d7f-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-11-21T16:04:00	betzgrp-wintermute.eecg.utoronto.ca	/home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	63888	99	130	378	508	1	260	308	14	14	196	clb	auto	23.3 MiB	0.07	836	35634	7872	13338	14424	62.4 MiB	0.06	0.00	30	1863	18	4.32e+06	2.46e+06	504535.	2574.16	0.99	
