/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  Copyright (C) 2019 - 2021 Xilinx, Inc.
 */

#ifndef _DT_BINDINGS_VERSAL_POWER_H
#define _DT_BINDINGS_VERSAL_POWER_H

#define PM_DEV_RPU0_0				(0x18110005U)
#define PM_DEV_RPU0_1				(0x18110006U)
#define PM_DEV_OCM_0				(0x18314007U)
#define PM_DEV_OCM_1				(0x18314008U)
#define PM_DEV_OCM_2				(0x18314009U)
#define PM_DEV_OCM_3				(0x1831400aU)
#define PM_DEV_TCM_0_A				(0x1831800bU)
#define PM_DEV_TCM_0_B				(0x1831800cU)
#define PM_DEV_TCM_1_A				(0x1831800dU)
#define PM_DEV_TCM_1_B				(0x1831800eU)
#define PM_DEV_USB_0				(0x18224018U)
#define PM_DEV_GEM_0				(0x18224019U)
#define PM_DEV_GEM_1				(0x1822401aU)
#define PM_DEV_SPI_0				(0x1822401bU)
#define PM_DEV_SPI_1				(0x1822401cU)
#define PM_DEV_I2C_0				(0x1822401dU)
#define PM_DEV_I2C_1				(0x1822401eU)
#define PM_DEV_CAN_FD_0				(0x1822401fU)
#define PM_DEV_CAN_FD_1				(0x18224020U)
#define PM_DEV_UART_0				(0x18224021U)
#define PM_DEV_UART_1				(0x18224022U)
#define PM_DEV_GPIO				(0x18224023U)
#define PM_DEV_TTC_0				(0x18224024U)
#define PM_DEV_TTC_1				(0x18224025U)
#define PM_DEV_TTC_2				(0x18224026U)
#define PM_DEV_TTC_3				(0x18224027U)
#define PM_DEV_SWDT_LPD				(0x18224028U)
#define PM_DEV_SWDT_FPD				(0x18224029U)
#define PM_DEV_OSPI				(0x1822402aU)
#define PM_DEV_QSPI				(0x1822402bU)
#define PM_DEV_GPIO_PMC				(0x1822402cU)
#define PM_DEV_I2C_PMC				(0x1822402dU)
#define PM_DEV_SDIO_0				(0x1822402eU)
#define PM_DEV_SDIO_1				(0x1822402fU)
#define PM_DEV_RTC				(0x18224034U)
#define PM_DEV_ADMA_0				(0x18224035U)
#define PM_DEV_ADMA_1				(0x18224036U)
#define PM_DEV_ADMA_2				(0x18224037U)
#define PM_DEV_ADMA_3				(0x18224038U)
#define PM_DEV_ADMA_4				(0x18224039U)
#define PM_DEV_ADMA_5				(0x1822403aU)
#define PM_DEV_ADMA_6				(0x1822403bU)
#define PM_DEV_ADMA_7				(0x1822403cU)
#define PM_DEV_AI				(0x18224072U)

#endif
