/**
  @page TIM_Synchronization TIM Synchronization mode example
  
  @verbatim
  ******************** (C) COPYRIGHT 2015 STMicroelectronics *******************
  * @file    TIM/TIM_Synchronization/readme.txt 
  * @author  MCD Application Team
  * @version V1.1.3
  * @date    15-December-2021
  * @brief   Description of the TIM Synchronization mode example.
  ******************************************************************************
  *
  * Copyright (c) 2015 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
   @endverbatim

@par Example Description 

This example shows how to synchronize TIM peripherals in cascade mode.
In this example three timers are used:

Timers synchronisation in cascade mode:

1/TIM2 is configured as Master Timer:
 - PWM Mode is used
 - The TIM2 Update event is used as Trigger Output

2/TIM3 is slave for TIM2
 - PWM Mode is used
 - The ITR1(TIM2) is used as input trigger 
 - Gated mode is used, so start and stop of slave counter
   are controlled by the Master trigger output signal(TIM2 update event).

The TIM2 counter clock is 72 MHz.

  The Master Timer TIM2 is running at TIM2 frequency :
  TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.25 KHz 
  and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.

  The TIM3 is running at:
  (TIM2 frequency)/ (TIM3 period + 1) = 28.125 KHz and a duty cycle equal 
  to TIM3_CCR1/(TIM3_ARR + 1) = 40%

  The TIM4 is running at:
  (TIM3 frequency)/ (TIM4 period + 1) = 7.031 Hz and a duty cycle equal 
  to TIM4_CCR1/(TIM4_ARR + 1) = 50% 

@par Directory contents 

  - TIM/TIM_Synchronization/stm32f30x_conf.h    Library Configuration file
  - TIM/TIM_Synchronization/stm32f30x_it.c      Interrupt handlers
  - TIM/TIM_Synchronization/stm32f30x_it.h      Interrupt handlers header file
  - TIM/TIM_Synchronization/main.c              Main program
  - TIM/TIM_Synchronization/system_stm32f30x.c  STM32F30x system source file
  
@note The "system_stm32f30x.c" is generated by an automatic clock configuration 
      system and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32F30x_Clock_Configuration_V1.0.0.xls" 
      provided with the AN4152 package available on <a href="http://www.st.com/internet/mcu/family/141.jsp">  ST Microcontrollers </a>
 
@par Hardware and Software environment

  - This example runs on STM32F303xC and STM32F303xE Devices.
  
  - This example has been tested with STMicroelectronics STM32303C-EVAL (STM32F30x)
    evaluation board and can be easily tailored to any other supported device 
    and development board.

  - STM32303C-EVAL Set-up
     - Connect the following pins to an oscilloscope to monitor the different 
      waveforms:
        - TIM2 CH1 (PA.00) 
        - TIM3 CH1 (PA.06)
        - TIM4 CH1 (PB.06)

@par How to use it ? 

In order to make the program work, you must do the following :
 - Copy all source files from this example folder to the template folder under
   Projects\STM32F30x_StdPeriph_Templates
 - Open your preferred toolchain 
 - Rebuild all files and load your image into target memory
 - Run the example


 */

