<ENTRY>
{
 "thisFile": "/group/dphi_cloud/jackiez/DPU_v3e_xo_gen_flow280/bit_gen/u280.xclbin.link_summary",
 "connectId": "",
 "serverToken": "",
 "timestamp": "0"
}
</ENTRY>
<ENTRY>
{
 "type": "ET_CmdStep",
 "dateTimestamp": "Tue Dec 28 15:42:31 2021",
 "timestampMillis": "1640677351098",
 "buildStep": {
  "cmdId": "b82cfeb6-d2bc-4128-805c-fd3dfb138583",
  "name": "v++",
  "logFile": "/group/dphi_cloud/jackiez/DPU_v3e_xo_gen_flow280/bit_gen/u280_imp/link/link.steps.log",
  "commandLine": "/proj/xbuilds/SWIP/2021.2_1021_0703/installs/lin64/Vitis/2021.2/bin/unwrapped/lnx64.o/v++  --vivado.prop \"run.__KERNEL__.{STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS}={-directive sdx_optimization_effort_high}\" --advanced.misc \"report=type report_timing_summary name impl_report_timing_summary_route_design_summary steps {route_design} runs {impl_1} options {-max_paths 10}\" --advanced.misc \"report=type report_timing_summary name impl_report_timing_summary_post_route_phys_opt_design_summary steps {post_route_phys_opt_design} runs {impl_1} options {-max_paths 10}\" -t hw --platform xilinx_u280_xdma_201920_3 --save-temps --temp_dir u280_imp -l --config ./constraints/cons.ini -o u280.xclbin ../release_u280_xo/DPUCAHX8H_3ENGINE.xo ../release_u280_xo/DPUCAHX8H_4ENGINE.xo ../release_u280_xo/DPUCAHX8H_5ENGINE.xo ",
  "args": [
   "-t",
   "hw",
   "--platform",
   "xilinx_u280_xdma_201920_3",
   "--save-temps",
   "--temp_dir",
   "u280_imp",
   "-l",
   "--config",
   "./constraints/cons.ini",
   "-o",
   "u280.xclbin",
   "../release_u280_xo/DPUCAHX8H_3ENGINE.xo",
   "../release_u280_xo/DPUCAHX8H_4ENGINE.xo",
   "../release_u280_xo/DPUCAHX8H_5ENGINE.xo"
  ],
  "iniFiles": [
   {
    "path": "/group/dphi_cloud/jackiez/DPU_v3e_xo_gen_flow280/bit_gen/constraints/cons.ini",
    "content": "\nkernel_frequency=0:300|1:100\n\nuser_ip_repo_paths=../DPUCAHX8H_SRC/DPU\n\n[advanced]\nparam=compiler.worstNegativeSlack=-1\nparam=compiler.errorOnHoldViolation=false\nparam=compiler.userPostSysLinkTcl=./constraints/sys_link_post.tcl\nmisc=solution_name=link\n\n[vivado]\nparam=project.writeIntermediateCheckpoints=1\nprop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore\nprop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore\nprop=run.impl_1.STEPS.INIT_DESIGN.TCL.POST=./constraints/init_design.post.tcl\nprop=run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=./constraints/opt_design.pre.tcl\nprop=run.impl_1.STEPS.OPT_DESIGN.TCL.POST=./constraints/opt_design.post.tcl\nprop=run.impl_1.STEPS.PLACE_DESIGN.TCL.POST=./constraints/place_design.post.tcl\nprop=run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-verbose -debug_log}\nprop=run.impl_1.STEPS.ROUTE_DESIGN.TCL.POST=./constraints/route_design.post.tcl\nprop=run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-verbose}\nprop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true\nprop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore\nprop=run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-verbose}\nprop=run.impl_1.STEPS.PHYS_OPT_DESIGN.TCL.POST=./constraints/phys_place_design.post.tcl\nprop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=NoTimingRelaxation\nprop=run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-tns_cleanup}\nprop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true\nprop=run.impl_1.{STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-verbose}\nprop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.TCL.POST=./constraints/phys_route_design.post.tcl\n\n[connectivity]\nnk=DPUCAHX8H_3ENGINE:1:dpu_0\nnk=DPUCAHX8H_4ENGINE:1:dpu_1\nnk=DPUCAHX8H_5ENGINE:1:dpu_2\nsp=dpu_0.DPU_AXI_0:HBM[00:31]\nsp=dpu_1.DPU_AXI_0:HBM[00:31]\nsp=dpu_1.DPU_AXI_3:HBM[00:31]\nsp=dpu_2.DPU_AXI_0:HBM[00:31]\nsp=dpu_2.DPU_AXI_1:HBM[00:31]\nsp=dpu_2.DPU_AXI_4:HBM[00:31]\nsp=dpu_0.DPU_AXI_I0:HBM[00:31]\nsp=dpu_1.DPU_AXI_I0:HBM[00:31]\nsp=dpu_2.DPU_AXI_I0:HBM[00:31]\nsp=dpu_0.DPU_AXI_1:HBM[00:31]\nsp=dpu_0.DPU_AXI_2:HBM[00:31]\nsp=dpu_1.DPU_AXI_1:HBM[00:31]\nsp=dpu_1.DPU_AXI_2:HBM[00:31]\nsp=dpu_2.DPU_AXI_2:HBM[00:31]\nsp=dpu_2.DPU_AXI_3:HBM[00:31]\nsp=dpu_0.DPU_AXI_W0:HBM[00:31]\nsp=dpu_0.DPU_AXI_W1:HBM[00:31]\nsp=dpu_1.DPU_AXI_W0:HBM[00:31]\nsp=dpu_1.DPU_AXI_W1:HBM[00:31]\nsp=dpu_2.DPU_AXI_W0:HBM[00:31]\nsp=dpu_2.DPU_AXI_W1:HBM[00:31]\n"
   }
  ],
  "cwd": "/group/dphi_cloud/jackiez/DPU_v3e_xo_gen_flow280/bit_gen"
 }
}
</ENTRY>
<ENTRY>
{
 "type": "ET_Status",
 "dateTimestamp": "Tue Dec 28 15:42:31 2021",
 "timestampMillis": "1640677351099",
 "status": {
  "cmdId": "b82cfeb6-d2bc-4128-805c-fd3dfb138583",
  "state": "CS_RUNNING"
 }
}
</ENTRY>
