PmodOLEDrgb IP
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Using the IP in Vivado
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A tutorial for using Pmod IP cores in Vivado is available [here](https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start).
At the step for connecting reference clocks, be sure to connect the IP's
ext_spi_clk port to a 50 MHz clock. The 50 MHz clock can be generated by either
the Clocking Wizard or the Memory Interface Generator (MIG). Instructions are
available for both approaches in the tutorial.

Demo Program in Xilinx SDK
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The demo program initializes and uses the PmodOLEDrgb to display strings of
different colors and a BMP image.
