PmodJSTK IP
============

Using the IP in Vivado
------------
A tutorial for using Pmod IP cores in  Vivado is available [here](https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start).
At the step for connecting reference clocks, be sure to connect the IP's
ext_spi_clk port to a 16 MHz clock. The 16 MHz clock can be generated by either
the Clocking Wizard or the Memory Interface Generator (MIG). Instructions are
available for both approaches in the tutorial.

Demo Program in Xilinx SDK
------------
The demo program reads the X and Y position of the joystick and prints those
values to the terminal. If the buttons on the JSTK are pressed, the adjacent LED
will turn red. If either of the buttons or the joystick button are pressed, a
message stating which of the buttons are pressed will be printed along with the
positional data.

To see text output from the example program, you will need to open a serial
terminal, such as TeraTerm. Settings for the terminal will vary depending on
your board.

For Zynq projects, apply the following settings:
- Baud rate: 115200
- Data bits: 8
- Parity:    none
- Stop bits: 1

For MicroBlaze projects, apply the settings according to the AXI Uartlite IP
configurations. These settings can be found by double clicking the AXI Uartlite
IP in the block design and clicking the IP Configuration tab. By default, these
settings are:
- Baud rate: 9600
- Data bits: 8
- Parity:    none
- Stop bits: 1
