David McKinnon

Embedded ML Engineer

mckinnondavidj@gmail.com

Redmond, WA

Notable Skills

Work History

Qualcomm - Senior Machine Learning Engineer

Nov 2023 - Present

Many ML models are not ready for running on NPUs (Qualcomm's Hexagon). My work focused on implementing graph passes and Ops to enable all the models in Qualcomm's AI Hub Models collection to run on Hexagon.

  • Graph passes in HexNN, involving tiling, memory location (eg VTCM), and memory formatting
  • Implementing ops in HVX and HMX assembly
  • Graph passes in ONNX Optimizer
  • Compiling and quantising open-source models for TFLite and QNN, including fixing incompatibilities
  • Released Qualcomm AI Hub and Qualcomm AI Hub Models

    • Tetra - ML Engineer

    May 2023 - Nov 2023 (acquired by Qualcomm Nov 2023)

    Many ML models are designed for PyTorch but not for TFLite or CoreML. My work focused on fixing incompatibilities to bridge this gap and optimise models for devices.

  • Implemented missing ML ops from pytorch in tensorflow and coreml, eg. multi-head attention
  • Implemented CoreML graph passes
  • Compiling and quantising open-source models for TFLite and QNN, including fixing incompatibilities

    • Microsoft - Software Engineer II

    Jan 2017 - Feb 2023

    I worked on many new and experimental features within the tracking framework of the Microsoft HoloLens, like tracking in visually constrained environments or non-inertial environments, and also developed analyses to measure tracking accuracy in these situations.

  • Shipped Windows Mixed Reality and HoloLens 2
  • Developed 6DoF QR code tracking on HoloLens ASIC, involving stereo triangulation and integrating into the map
  • Developed visual SLAM in a non-inertial reference frame
  • Analysis of tracking-accuracy-measurement methods: comparing optitrack to ndi optotrack to Vive lighthouses, including considerations for when the reference frame was moving too.
  • Constellation-based SLAM for tracking in the dark or environmentally constrained scenarios.
  • Designed and developed test architecture for assessing hologram stability across visual tracking and display pipeline for build validation.
  • Optimising the visual-inertial tracker for cDSP blocks in the XR2 SoC. Involved researching the cDSP architecture, porting existing algorithms, and attempts at hardware-optimised mathematics both by hand and auto-done by compiler.

    • Research experience

    Personal Work

    Education and Skills

    Patents

    Links