.. zephyr:board:: titanium_ti60_f225

Overview
********

The Efinix Titanium Ti60 F225 development kit contains a Ti60 FPGA, which is fabricated on a 16nm process and deliver
high performance with the lowest possible power on a small physical size. In addition, Efinix offers Sapphire SoC IP,
which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set and extension.
Using the Efinity IP Manager, you can configure the SoC to include only the peripherals that you require.

Board block diagram
*******************

.. figure:: img/Ti60-BGA225-board-block-diagram.jpg
   :align: center
   :alt: titanium_ti60_f225_board-block-diagram

More information can be found on `Ti60F225`_ website.

Sapphire SoC setup on the FPGA guide
*************************************

Guide to setup the SoC found at `Efinix-Zephyr`_

Building
********

Build applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).

.. zephyr-app-commands::
   :zephyr-app: samples/hello_world
   :board: titanium_ti60_f225
   :goals: build

Flashing
********

Flashing the binary into SPI NOR flash requires Efinity programmer, Please find the guide at `Efinix-Zephyr`_

.. note::

   The Zephyr RTOS has been verified using the SoC bitstream generated by Efinity IDE v2022.2.322.

References
**********

.. target-notes::

.. _Ti60F225: https://www.efinixinc.com/products-devkits-titaniumti60f225.html
.. _Efinix-Zephyr: https://github.com/Efinix-Inc/zephyr-efinix
