SECTIONS
{
    __vectors_table = 0x0;
    Reset_Handler = 0x101;
    NMI_Handler = 0x105;
    HardFault_Handler = 0x109;
    MemManage_Handler = 0x10d;
    BusFault_Handler = 0x111;
    DiagVSprintf = 0x115;
    DiagPrintf = 0x475;
    DiagPrintfD = 0x4b9;
    DiagSPrintf = 0x4dd;
    DiagSnPrintf = 0x501;
    cmd_write_word = 0x8d9;
    cmd_dump_word = 0x91d;
    cmd_flash = 0x9f9;
    cmd_efuse = 0xf91;
    cmd_rom_table = 0x12e9;
    Rand = 0x12f5;
    Rand_Arc4 = 0x1375;
    RandBytes_Get = 0x13a9;
    io_assert_failed = 0x13f1;
    BKUP_Write = 0x1411;
    BKUP_Read = 0x1435;
    BKUP_Set = 0x1455;
    BKUP_Clear = 0x147d;
    BOOT_Reason = 0x14a5;
    DelayNop = 0x14b5;
    DelayUs = 0x14c3;
    DelayMs = 0x1505;
    EFUSEPowerSwitch = 0x1519;
    EFUSERead8 = 0x159d;
    EFUSEWrite8 = 0x1661;
    EFUSE_PG_Packet = 0x1731;
    EFUSE_LogicalMap_Read = 0x1965;
    EFUSE_LogicalMap_Write = 0x1a71;
    FLASH_SW_CS_Control = 0x1c51;
    FLASH_SetSpiMode = 0x1c91;
    FLASH_RxCmd = 0x1d1d;
    FLASH_WaitBusy = 0x1d89;
    FLASH_RxData = 0x1df5;
    FLASH_TxCmd = 0x1ebd;
    FLASH_WriteEn = 0x1f3d;
    FLASH_TxData256B = 0x1f61;
    FLASH_TxData12B = 0x2049;
    FLASH_SetStatus = 0x2129;
    FLASH_Erase = 0x2147;
    FLASH_DeepPowerDown = 0x21b9;
    FLASH_SetStatusBits = 0x2205;
    FLASH_StructInit_Micron = 0x22a5;
    FLASH_StructInit_MXIC = 0x2333;
    FLASH_StructInit_GD = 0x23bd;
    FLASH_StructInit = 0x2451;
    FLASH_Init = 0x24e1;
    GDMA_StructInit = 0x2559;
    GDMA_SetLLP = 0x2579;
    GDMA_ClearINTPendingBit = 0x25e1;
    GDMA_ClearINT = 0x26ad;
    GDMA_INTConfig = 0x2775;
    GDMA_Cmd = 0x286d;
    GDMA_Init = 0x28b9;
    GDMA_ChCleanAutoReload = 0x29e5;
    GDMA_SetSrcAddr = 0x2a41;
    GDMA_GetSrcAddr = 0x2a75;
    GDMA_GetDstAddr = 0x2aa5;
    GDMA_SetDstAddr = 0x2ad9;
    GDMA_SetBlkSize = 0x2b0d;
    GDMA_GetBlkSize = 0x2b4d;
    GDMA_ChnlRegister = 0x2b85;
    GDMA_ChnlUnRegister = 0x2bc9;
    GDMA_ChnlAlloc = 0x2c01;
    GDMA_ChnlFree = 0x2c85;
    GDMA_GetIrqNum = 0x2ce5;
    GPIO_INTMode = 0x2d15;
    GPIO_INTConfig = 0x2da1;
    GPIO_INTHandler = 0x2dcd;
    GPIO_Direction = 0x2e71;
    GPIO_Init = 0x2e9d;
    GPIO_DeInit = 0x2f19;
    GPIO_ReadDataBit = 0x2f7d;
    GPIO_WriteBit = 0x2f9d;
    GPIO_PortDirection = 0x2fc9;
    GPIO_PortRead = 0x2fed;
    GPIO_PortWrite = 0x2ffd;
    GPIO_UserRegIrq = 0x3015;
    IPC_INTConfig = 0x3045;
    IPC_IERSet = 0x3057;
    IPC_IERGet = 0x305b;
    IPC_INTRequest = 0x305f;
    IPC_INTClear = 0x3067;
    IPC_INTGet = 0x306f;
    IPC_CPUID = 0x3073;
    IPC_SEMGet = 0x307d;
    IPC_SEMFree = 0x30c5;
    IPC_INTHandler = 0x3129;
    IPC_INTUserHandler = 0x3161;
    LOGUART_StructInit = 0x3199;
    LOGUART_Init = 0x31b1;
    LOGUART_PutChar = 0x31f1;
    LOGUART_GetChar = 0x3221;
    LOGUART_Readable = 0x3239;
    LOGUART_GetIMR = 0x324d;
    LOGUART_SetIMR = 0x3259;
    LOGUART_WaitBusy = 0x3265;
    LOGUART_SetBaud = 0x3285;
    LOGUART_SetBaud_FromFlash = 0x32c9;
    LOGUART_DiagInit = 0x32e9;
    mpu_enable = 0x3359;
    mpu_disable = 0x3371;
    mpu_init = 0x3385;
    mpu_set_mem_attr = 0x33ad;
    mpu_region_cfg = 0x3401;
    mpu_entry_free = 0x34ed;
    mpu_entry_alloc = 0x34f9;
    RSIP_Cmd = 0x3511;
    RSIP_OTF_init = 0x3531;
    RSIP_OTF_Cmd = 0x3595;
    RSIP_OTF_Mask = 0x35a9;
    RSIP_KEY_Request = 0x35e9;
    RSIP_MMU_Config = 0x3625;
    RSIP_MMU_Cmd = 0x3649;
    PAD_DrvStrength = 0x3665;
    PAD_PullCtrl = 0x3685;
    PAD_CMD = 0x36b1;
    Pinmux_Config = 0x36dd;
    Pinmux_ConfigGet = 0x36fd;
    Pinmux_UartLogCtrl = 0x370d;
    Pinmux_SpicCtrl = 0x3749;
    simulation_bit_index = 0x3801;
    simulation_stage_set = 0x3815;
    SYSTIMER_Init = 0x3839;
    SYSTIMER_TickGet = 0x3885;
    SYSTIMER_GetPassTime = 0x3899;
    RTIM_TimeBaseStructInit = 0x38c5;
    RTIM_Cmd = 0x38db;
    RTIM_GetCount = 0x398d;
    RTIM_INTConfig = 0x3a21;
    RTIM_INTClear = 0x3ad1;
    RTIM_TimeBaseInit = 0x3b65;
    RTIM_DeInit = 0x3cad;
    RTIM_INTClearPendingBit = 0x3d51;
    RTIM_GetFlagStatus = 0x3ded;
    RTIM_GetINTStatus = 0x3f0d;
    UART_DeInit = 0x4039;
    UART_StructInit = 0x403f;
    UART_BaudParaGetFull = 0x405b;
    UART_BaudParaGet = 0x408d;
    UART_SetBaud = 0x40b1;
    UART_SetBaudExt = 0x4141;
    UART_SetRxLevel = 0x41b5;
    UART_RxCmd = 0x41dd;
    UART_Writable = 0x41ed;
    UART_Readable = 0x41f5;
    UART_CharPut = 0x41fd;
    UART_CharGet = 0x4201;
    UART_ReceiveData = 0x4207;
    UART_SendData = 0x422d;
    UART_ReceiveDataTO = 0x4251;
    UART_SendDataTO = 0x4289;
    UART_RxByteCntClear = 0x42c1;
    UART_RxByteCntGet = 0x42cd;
    UART_BreakCtl = 0x42d3;
    UART_ClearRxFifo = 0x42e7;
    UART_Init = 0x4307;
    UART_ClearTxFifo = 0x43ad;
    UART_INTConfig = 0x43b7;
    UART_IntStatus = 0x43c9;
    UART_ModemStatusGet = 0x43cd;
    UART_LineStatusGet = 0x43d1;
    UART_WaitBusy = 0x43d5;
    BOOT_ROM_CM4PON = 0x43f9;
    BOOT_ROM_OSC131_Enable = 0x44f1;
    BOOT_ROM_ResetVsr = 0x4505;
    EXT32K_Cmd = 0x49d1;
    XTAL_ClkGet = 0x49f9;
    CPU_ClkSet = 0x4a11;
    CPU_ClkGet = 0x4a25;
    FLASH_ClockDiv = 0x4a49;
    FLASH_CalibrationInit = 0x4ae5;
    FLASH_Calibration500MPSCmd = 0x4afd;
    FLASH_CalibrationPhase = 0x4b1d;
    FLASH_CalibrationPhaseIdx = 0x4ba9;
    FLASH_CalibrationNewCmd = 0x4bc1;
    FLASH_CalibrationNew = 0x4bfd;
    FLASH_Calibration = 0x4dd1;
    RCC_PeriphClockCmd = 0x4f09;
    RCC_PeriphClockSource_RTC = 0x4f89;
    RCC_PeriphClockSource_I2C = 0x4fd9;
    RCC_PeriphClockSource_QDEC = 0x4ff9;
    RCC_PeriphClockSource_UART = 0x5019;
    SYSCFG_GetChipInfo = 0x5091;
    SYSCFG_CUTVersion = 0x509d;
    SYSCFG_AutoLoadDone = 0x50ad;
    SYSCFG_TRP_LDOMode = 0x50bd;
    SYSCFG_TRP_UARTImage = 0x50cd;
    SYSCFG_TRP_ICFG = 0x50dd;
    SYSCFG_ROMINFO_Get = 0x50e9;
    SYSCFG_ROMINFO_Set = 0x50f5;
    INT_HardFault_C = 0x5299;
    INT_NMI = 0x536d;
    INT_HardFault = 0x5389;
    INT_MemManage = 0x53a1;
    INT_BusFault = 0x53bd;
    INT_UsageFault = 0x53d9;
    irq_table_init = 0x53f5;
    irq_enable = 0x5559;
    irq_disable = 0x5575;
    irq_set_priority = 0x5599;
    irq_get_priority = 0x55f9;
    irq_set_pending = 0x563d;
    irq_get_pending = 0x5659;
    irq_clear_pending = 0x567d;
    irq_register = 0x5699;
    irq_unregister = 0x5711;
    shell_array_init = 0x572d;
    shell_get_argc = 0x573b;
    shell_get_argv = 0x5767;
    shell_cmd_chk = 0x5831;
    shell_uart_irq_rom = 0x58f5;
    shell_init_rom = 0x59ad;
    shell_task_rom = 0x5a1d;
    shell_rom = 0x5a45;
    xmodem_img_rxbuffer = 0x5ae9;
    xmodem_uart_init = 0x60f5;
    xmodem_uart_deinit = 0x618d;
    xmodem_uart_port_init = 0x61a1;
    xmodem_uart_port_deinit = 0x61d5;
    xmodem_uart_readable = 0x6221;
    xmodem_uart_writable = 0x6239;
    xmodem_uart_getc = 0x6251;
    xmodem_uart_putc = 0x6275;
    xmodem_uart_putdata = 0x628d;
    xmodem_uart_getc_to = 0x62a9;
    xmodem_uart_clean_rx = 0x62f1;
    xmodem_img_write = 0x6331;
    xmodem_img_download = 0x634d;
    _char2num = 0x63c1;
    _2char2dec = 0x63ed;
    _2char2hex = 0x645d;
    _memchr = 0x64c5;
    _memcmp = 0x6545;
    _memcpy = 0x6591;
    _memmove = 0x6611;
    _memset = 0x66ad;
    _vsscanf = 0x67d1;
    _sscanf = 0x6c51;
    _stratoi = 0x6c69;
    _strcat = 0x6cc1;
    _strchr = 0x6d11;
    _strcmp = 0x6de9;
    _strcpy = 0x6e49;
    _stricmp = 0x6e91;
    _strlen = 0x6ec5;
    _strncat = 0x6f29;
    _strncmp = 0x6f8d;
    _strncpy = 0x7019;
    _strnlen = 0x7081;
    _strpbrk = 0x70a5;
    _strsep = 0x70d1;
    _strstr = 0x73cd;
    _strtoull = 0x75d5;
    _strtoll = 0x76d5;
    _strtok = 0x76f5;
    __strtok_r = 0x7705;
    _strtok_r = 0x7761;
    _strtol_r = 0x776d;
    _strtol = 0x7899;
    _strtoul_r = 0x78a1;
    _strtoul = 0x79d9;
    _strupr = 0x79e1;
    Write778_8721D_ROM = 0x79fd;
    DacSwing_8721D_ROM = 0x7a3d;
    InitBTMailbox_8721D_ROM = 0x7a61;
    BTMailboxRetry_8721D_ROM = 0x7ae9;
    C2HBTInfo_8721D_ROM = 0x7b39;
    C2HBTLoopback_8721D_ROM = 0x7be5;
    C2HBTMpRpt_8721D_ROM = 0x7c21;
    BTNullSetting_8721D_ROM = 0x7c91;
    IssueBTQNull_8721D_ROM = 0x7cf9;
    WlanActCtrl_8721D_ROM = 0x7d9d;
    ChangeCoexTable_8721D_ROM = 0x7dd5;
    InitBTCoexTimer_8721D_ROM = 0x7e15;
    FlexibleExtensionDecision_8721D_ROM = 0x7e31;
    BT_TDMA_Slot_Operation_1and4_8721D_ROM = 0x7f95;
    BT_TDMA_Slot_Operation_2and5_8721D_ROM = 0x80c9;
    BT_TDMA_Slot_Operation_0and3_8721D_ROM = 0x81fd;
    InitBTypeTDMA2_8721D_ROM = 0x8341;
    BTypeTDMABCNEarly_8721D_ROM = 0x8361;
    BTypeTDMATBTThdl_8721D_ROM = 0x8445;
    BTypeTDMATimeOuthdl_8721D_ROM = 0x8491;
    BTRoleChangeTimerHDL_8721D_ROM = 0x84e9;
    BTRoleChangeTBTTHDL_8721D_ROM = 0x8509;
    MailboxINTHDL_8721D_ROM = 0x8559;
    H2CInQueue_8721D_ROM = 0x8701;
    H2CDeQueue_8721D_ROM = 0x87fd;
    InitC2H_8721D_ROM = 0x8855;
    WaitC2HOk_8721D_ROM = 0x8879;
    C2HPKTRxDESC_8721D_ROM = 0x88b5;
    FillC2HContant_8721D_ROM = 0x890d;
    IssueC2HPKT_8721D_ROM = 0x8949;
    C2HDeQueue_8721D_ROM = 0x8999;
    C2HInQueue_8721D_ROM = 0x89e9;
    PktBufAccessCtrl_8721D_ROM = 0x8a3d;
    FillMailbox_8721D_ROM = 0x8aad;
    WL2BTMailbox_8721D_ROM = 0x8b69;
    H2CHDL_BTInfo_8721D_ROM = 0x8bfd;
    H2CHDL_ForceBTTxpwr_8721D_ROM = 0x8c81;
    H2CHDL_BTIgnoreWlanAct_8721D_ROM = 0x8c95;
    H2CHDL_DACSwingValue_8721D_ROM = 0x8d05;
    H2CHDL_AntSelReverse_8721D_ROM = 0x8d41;
    H2CHDL_WLOpmode_8721D_ROM = 0x8d55;
    H2CHDL_BTMpH2C_8721D_ROM = 0x8dc5;
    H2CHDL_BTControl_8721D_ROM = 0x8e7d;
    H2CHDL_BTWifiCtrl_8721D_ROM = 0x8ee5;
    H2CHDL_BT_Page_Scan_Interval_8721D_ROM = 0x8f8d;
    H2CHDL_WLCalibration_8721D_ROM = 0x8fb1;
    H2CHDL_GNT_BT_CTRL_8721D_ROM = 0x9021;
    H2CHDL_BT_ONLY_TEST_8721D_ROM = 0x906d;
    H2CHDL_BT_Init_Param_8721D_ROM = 0x9099;
    CheckMaxMacidNum_8721D_ROM = 0x9119;
    SetMediaStatus_8721D_ROM = 0x9169;
    GetMediaStatus_8721D_ROM = 0x919d;
    WaitDDMARDY = 0x91b5;
    InitDDMA = 0x91e5;
    ChkDDMAChksum = 0x92a5;
    CheckDDMADone = 0x92e9;
    FwlbkLLTWrite_8721D_ROM = 0x9311;
    FwlbkCheckRxPayload_8721D_ROM = 0x935d;
    FwlbkModeAFElbk_8721D_ROM = 0x95bd;
    FwlbkMcuPollMgq_8721D_ROM = 0x972d;
    FwlbkMode_8721D_ROM = 0x9789;
    FwlbkHWInitialLLT_8721D_ROM = 0x9911;
    FwlbkDbgPrtU16_8721D_ROM = 0x9981;
    FwlbkPreparePkt_8721D_ROM = 0x998d;
    FwlbkModeSel_8721D_ROM = 0x9a99;
    FwlbkSetCAM_8721D_ROM = 0x9b31;
    FwlbkUpdateParam_8721D_ROM = 0x9bd5;
    FwlbkModeMaclbk_8721D_ROM = 0x9c21;
    FwlbkModeTx_8721D_ROM = 0x9c31;
    FwlbkModeTxNoCheck_8721D_ROM = 0x9c39;
    FwlbkModeSecTest_8721D_ROM = 0x9c41;
    OnWpa_offload_8721D_ROM = 0x9db9;
    wpa_supplicant_process_1_of_2_8721D_ROM = 0x9f51;
    wpa_supplicant_decrypt_key_data_8721D_ROM = 0x9f71;
    wpa_supplicant_send_2_of_2_8721D_ROM = 0xa131;
    WriteCAM_8721D_ROM = 0xa3bd;
    ReadCAM_8721D_ROM = 0xa41d;
    write_cam_wow_8721D_ROM = 0xa481;
    AesTkipIvFun_8721D_ROM = 0xa531;
    WepIvFun_8721D_ROM = 0xa581;
    AppendTkipMIC_8721D_ROM = 0xa5bd;
    RTmemcmpBackward_8721D_ROM = 0xa6a9;
    AssignIvToKeyRsc_8721D_ROM = 0xa6cf;
    AssignKeyRscToIV_8721D_ROM = 0xa6fd;
    AesTkipIvCheck_8721D_ROM = 0xa73f;
    WepIvCheck_8721D_ROM = 0xa7b1;
    ReadGTKData_8721D_ROM = 0xa7ed;
    ClrAllFWUsedIMR_8721D_ROM = 0xa811;
    ClrAllFWUsedISR_8721D_ROM = 0xa875;
    CheckFWLBKEnable_8721D_ROM = 0xa8d9;
    UpdateISRWlan_8721D = 0xa8ed;
    UpdateISRFT_8721D = 0xa9a5;
    getSumValue_8721D_ROM = 0xaa01;
    getCheckSum_8721D_ROM = 0xaa4d;
    AESUnwrapSwap_8721D_ROM = 0xaadd;
    FillParameterIpsec_8721D_ROM = 0xab2d;
    FillMichaelPacketInfo_8721D_ROM = 0xab51;
    AesUnwrapIpsec_8721D_ROM = 0xab79;
    HmacSha1Ipsec_8721D_ROM = 0xabfd;
    HmcMd5Ipsec_8721D_ROM = 0xac5d;
    TkipMicIpsec_8721D_ROM = 0xacbd;
    RC4Ipsec_8721D_ROM = 0xadcd;
    IPSecDataIn_8721D_ROM = 0xae9d;
    IPSecDataOut_8721D_ROM = 0xaeb1;
    IPSecFillDesrciptor_8721D_ROM = 0xaec5;
    IPSWriteDescriptorIO_8721D_ROM = 0xaeef;
    IPSecDesrciptor_8721D_ROM = 0xaf09;
    IPSecWriteDataIOMode_8721D_ROM = 0xaf1d;
    IPSecSetExMemoryAddr_8721D_ROM = 0xaf85;
    IPSecSetDescAddr_8721D_ROM = 0xaf99;
    IPSecGetDataIOMode_8721D_ROM = 0xafad;
    IPSecSetOPMode_8721D_ROM = 0xb009;
    IPSecEngine_8721D_ROM = 0xb085;
    Aes128EncIpsec_8721D_ROM = 0xb19d;
    AESEncrypt128_8721D_ROM = 0xb1fd;
    Aes128DecIpsec_8721D_ROM = 0xb24d;
    AESDecrypt128_8721D_ROM = 0xb2ad;
    AES_CMAC_GenerateSubKey_1W_8721D_ROM = 0xb2fd;
    AES_CMAC_1W_8721D_ROM = 0xb3a1;
    AES_KeyExpansion_1W_8721D_ROM = 0xb491;
    AES_Encrypt_1W_8721D_ROM = 0xb595;
    ChangeTransmiteRate_8721D_ROM = 0xb791;
    PowerBitSetting_8721D_ROM = 0xb815;
    IssuePSPoll_8721D_ROM = 0xb87d;
    ChkandChangePS_8721D_ROM = 0xb8bd;
    IssueQNull_8721D_ROM = 0xb94d;
    CTS2SelfSetting_8721D_ROM = 0xb9e1;
    IssueCTS2Self_8721D_ROM = 0xb9fd;
    CheckCPUMGQEmpty_8721D_ROM = 0xba89;
    IssueRsvdPagePacketSetting_8721D_ROM = 0xbac9;
    ReadRxBuff_8721D_ROM = 0xbba1;
    PHY_InitBBRFRegDef_8721D = 0xbbc5;
    CheckBBRWIsStable_8721D = 0xbbf1;
    PHY_QueryBBReg_8721D = 0xbc45;
    PHY_SetBBReg_8721D = 0xbc9d;
    PHY_RFSerialRead_8721D = 0xbcf9;
    PHY_RFSerialWrite_8721D = 0xbd8d;
    PHY_QueryRFReg_8721D = 0xbda9;
    PHY_SetRFReg_8721D = 0xbdb1;
    SetSmartPSTimer_8721D_ROM = 0xbdb9;
    SetPwrStateReg_8721D_ROM = 0xbe15;
    ResetPSParm_8721D_ROM = 0xbe89;
    ChkTxQueueIsEmpty_8721D_ROM = 0xbec5;
    Legacy_PS_Setting_8721D_ROM = 0xbee9;
    PSModeSetting_8721D_ROM = 0xbf61;
    ConfigListenBeaconPeriod_8721D_ROM = 0xbff5;
    PSSetMode_8721D_ROM = 0xc035;
    PS_S2ToS3State_8721D_ROM = 0xc085;
    PS_S2ToS0State_8721D_ROM = 0xc109;
    PS_S3ToS2orS0State_8721D_ROM = 0xc139;
    PS_S0ToS1State_8721D_ROM = 0xc1a1;
    PS_S1ToS0orS2State_8721D_ROM = 0xc229;
    PS_S2ToS4State_8721D_ROM = 0xc299;
    PS_S2ToS5State_8721D_ROM = 0xc2ed;
    PS_S5ToS2State_8721D_ROM = 0xc329;
    PS_S4ToS2State_8721D_ROM = 0xc365;
    SmartPS2InitTimerAndToGetRxPkt_8721D_ROM = 0xc3a1;
    SetBcnEarlyAndTimeout_8721D_ROM = 0xc3e9;
    EnlargeBcnEarlyAndTimeout_8721D_ROM = 0xc48d;
    ResetBcnEarlyAdjustParm_8721D_ROM = 0xc4e1;
    PS_S0ToS6State_8721D_ROM = 0xc51d;
    PS_S6ToS0State_8721D_ROM = 0xc555;
    Set_arfr_8721D_ROM = 0xc58d;
    InitRAInfo_8721D_ROM = 0xc5e9;
    C2H_RA_Rpt_8721D_ROM = 0xc735;
    check_rate_8721D_ROM = 0xc76d;
    RateUp_search_RateMask_8721D_ROM = 0xc795;
    RateDown_search_RateMask_8721D_ROM = 0xc7cd;
    RateDownTrying_8721D_ROM = 0xc825;
    Count_Ratio_8721D_ROM = 0xc899;
    ArfrRefresh_8721D_ROM = 0xc907;
    H2CHDL_Set_MACID_Config_8721D_ROM = 0xca89;
    H2CHDL_SetRssiSingle_8721D_ROM = 0xcb85;
    ODM_H2C_RADebugMonitor_8721D_ROM = 0xcbb5;
    C2H_RA_Dbg_code_en_8721D_ROM = 0xcc99;
    InitialRateByRssi_8721D_ROM = 0xcd01;
    H2CHDL_Set_FW_Trace_en_8721D_ROM = 0xcd71;
    H2CHDL_APReqTxrpt_8721D_ROM = 0xcdad;
    H2CHDL_InitRateCollect_8721D_ROM = 0xcf15;
    Pkt_Num_shift_8721D_ROM = 0xcf7d;
    PT_update_8721D_ROM = 0xcf95;
    ResetTxrpt_8721D_ROM = 0xcfad;
    PsuseTxrpt_8721D_ROM = 0xcfe5;
    GetTxrptStatistic_8721D_ROM = 0xcff9;
    PollingReg_8721D_ROM = 0xd0e1;
    WritePONReg_8721D_ROM = 0xd121;
    ReadPONReg_8721D_ROM = 0xd12d;
    InitGTimer32us_8721D_ROM = 0xd13d;
    InitGTimer1ms_8721D_ROM = 0xd17d;
    setwlanimr_8721D_ROM = 0xd1d1;
    clrwlanimr_8721D_ROM = 0xd1ed;
    setwlanimr2_8721D_ROM = 0xd209;
    clrwlanimr2_8721D_ROM = 0xd225;
    setftimr_8721D_ROM = 0xd241;
    clrftimr_8721D_ROM = 0xd25d;
    GetIV = 0xd279;
    GetIVLenAndSecurityType_8721D_ROM = 0xd2a5;
    GetMACHeaderLen_8721D_ROM = 0xd2e9;
    UpdateIV_8721D_ROM = 0xd309;
    ROM_SIM_ENABLE = 0x20000;
    SPIC_CALIB_PATTERN = 0x20064;
    PORT_AB = 0x20080;
    OTF_IV_ENC = 0x20088;
    ROM_IMG1_VALID_PATTEN = 0x20098;
    BAUDRATE_TABLE = 0x2013c;
    FWLBK_LEN = 0x201cc;
    FWLBK_TXDESC = 0x201d4;
    FWLBK_HEADER_UC = 0x201fc;
    FWLBK_HEADER = 0x20214;
    CAM_DATA0 = 0x2022c;
    CAM_DATA1 = 0x20240;
    CAM_DATA2 = 0x20244;
    CAM_TYPE = 0x20258;
    CAM_DATA2_WAPI = 0x2025d;
    FWLBK_DATARATE = 0x20261;
    Const_Zero = 0x2026c;
    Const_Rb = 0x2027c;
    aes_rcon = 0x2028c;
    aes_sbox_enc = 0x202b8;
    aes_mul_2 = 0x203b8;
    aes_mul_3 = 0x204b8;
    __rom_bss_start__ = 0x80000;
    NewVectorTable = 0x80000;
    UserIrqFunTable = 0x800c0;
    UserIrqDataTable = 0x80140;
    ConfigDebugClose = 0x801c0;
    ConfigDebugBuffer = 0x801c4;
    ConfigDebugBufferGet = 0x801c8;
    ConfigDebug = 0x801cc;
    rand_first = 0x801dc;
    rand_seed = 0x801e0;
    RBSS_UDELAY_DIV = 0x801f4;
    flash_init_para = 0x801f8;
    GDMA_Reg = 0x80258;
    PortA_IrqHandler = 0x8025c;
    PortA_IrqData = 0x802dc;
    PortB_IrqHandler = 0x8035c;
    PortB_IrqData = 0x803dc;
    IPC_IrqHandler = 0x8045c;
    IPC_IrqData = 0x804dc;
    IS_FPGA_VERIF = 0x8055c;
    NEW_CALIBREATION_END = 0x80560;
    shell_argv_array = 0x80568;
    shell_ctl = 0x805a8;
    shell_recv_all_data_onetime = 0x805cc;
    shell_buf = 0x805d0;
    xmodem_ctrl = 0x80654;
    xmodem_uartx = 0x80660;
    mpu_entry_register = 0x80664;
    FWLBK_CTL_H = 0x8066c;
    FWLBK_SeqNum = 0x8066e;
    FWLBK_CTL_L = 0x80670;
    FWLBK_CTL_EXT = 0x80671;
    FwlbkModeAFElbk_8721D_PTR = 0x80674;
    FwlbkModeSecTest_8721D_PTR = 0x80678;
    FwlbkModeMaclbk_8721D_PTR = 0x8067c;
    FwlbkModeTx_8721D_PTR = 0x80680;
    FwlbkModeTxNoCheck_8721D_PTR = 0x80684;
    FwlbkMcuPollMgq_8721D_PTR = 0x80688;
    FwlbkUpdateParam_8721D_PTR = 0x8068c;
    FwlbkSetCAM_8721D_PTR = 0x80690;
    FwlbkCheckRxPayload_8721D_PTR = 0x80694;
    FwlbkModeSel_8721D_PTR = 0x80698;
    FwlbkPreparePkt_8721D_PTR = 0x8069c;
    FwlbkMode_8721D_PTR = 0x806a0;
    FwlbkHWInitialLLT_8721D_PTR = 0x806a4;
    FwlbkLLTWrite_8721D_PTR = 0x806a8;
    FwlbkDbgPrtU16_8721D_PTR = 0x806ac;
    AES_Encrypt_1W_8721D_PTR = 0x806b0;
    AES_CMAC_1W_8721D_PTR = 0x806b4;
    AES_CMAC_GenerateSubKey_1W_8721D_PTR = 0x806b8;
    AES_KeyExpansion_1W_8721D_PTR = 0x806bc;
    AESDecrypt128_8721D_PTR = 0x806c0;
    AESEncrypt128_8721D_PTR = 0x806c4;
    FillMichaelPacketInfo_8721D_PTR = 0x806c8;
    FillParameterIpsec_8721D_PTR = 0x806cc;
    Aes128DecIpsec_8721D_PTR = 0x806d0;
    Aes128EncIpsec_8721D_PTR = 0x806d4;
    TkipMicIpsec_8721D_PTR = 0x806d8;
    RC4Ipsec_8721D_PTR = 0x806dc;
    HmcMd5Ipsec_8721D_PTR = 0x806e0;
    HmacSha1Ipsec_8721D_PTR = 0x806e4;
    AESUnwrapSwap_8721D_PTR = 0x806e8;
    AesUnwrapIpsec_8721D_PTR = 0x806ec;
    IPSecSetDescAddr_8721D_PTR = 0x806f0;
    IPSecSetExMemoryAddr_8721D_PTR = 0x806f4;
    IPSecEngine_8721D_PTR = 0x806f8;
    IPSecSetOPMode_8721D_PTR = 0x806fc;
    IPSecGetDataIOMode_8721D_PTR = 0x80700;
    IPSecWriteDataIOMode_8721D_PTR = 0x80704;
    IPSecDesrciptor_8721D_PTR = 0x80708;
    IPSWriteDescriptorIO_8721D_PTR = 0x8070c;
    IPSecFillDesrciptor_8721D_PTR = 0x80710;
    IPSecDataOut_8721D_PTR = 0x80714;
    IPSecDataIn_8721D_PTR = 0x80718;
    getCheckSum_8721D_PTR = 0x8071c;
    getSumValue_8721D_PTR = 0x80720;
    AssignKeyRscToIV_Ptr = 0x80724;
    AssignIvToKeyRsc_Ptr = 0x80728;
    WepIvCheck_Ptr = 0x8072c;
    AesTkipIvCheck_Ptr = 0x80730;
    RTmemcmpBackward_Ptr = 0x80734;
    AppendTkipMIC_Ptr = 0x80738;
    ReadGTKData_Ptr = 0x8073c;
    ReadCAM_Ptr = 0x80740;
    WriteCAM_Ptr = 0x80744;
    write_cam_wow_Ptr = 0x80748;
    wpa_supplicant_send_2_of_2_Ptr = 0x8074c;
    wpa_supplicant_decrypt_key_data_Ptr = 0x80750;
    wpa_supplicant_process_1_of_2_Ptr = 0x80754;
    OnWpa_offload_Ptr = 0x80758;
    WepIvFun_Ptr = 0x8075c;
    AesTkipIvFun_Ptr = 0x80760;
    GetIVLenAndSecurityType_Ptr = 0x80764;
    GetMACHeaderLen_Ptr = 0x80768;
    updateCheckSumVer2_Ptr = 0x8076c;
    UpdateIV_Ptr = 0x80770;
    WakeUpHost_Ptr = 0x80774;
    PollingReg_8721D_Ptr = 0x80778;
    InitGTimer1ms_Ptr = 0x8077c;
    InitGTimer32us_Ptr = 0x80780;
    IssueRsvdPagePacketSetting_Ptr = 0x80784;
    ResetBcnEarlyAdjustParm_Ptr = 0x80788;
    EnlargeBcnEarlyAndTimeout_Ptr = 0x8078c;
    SetBcnEarlyAndTimeout_Ptr = 0x80790;
    PS_S2ToS0State_Ptr = 0x80794;
    ConfigListenBeaconPeriod_Ptr = 0x80798;
    IssueNullData_Ptr = 0x8079c;
    ChangeTransmiteRate_Ptr = 0x807a0;
    PowerBitSetting_Ptr = 0x807a4;
    IssueQNull_Ptr = 0x807a8;
    ReadRxBuff_Ptr = 0x807ac;
    IssuePSPoll_Ptr = 0x807b0;
    ChkandChangePS_Ptr = 0x807b4;
    IssueCTS2Self_Ptr = 0x807b8;
    WriteTxPauseWithMask_Ptr = 0x807bc;
    WriteTxPause_Ptr = 0x807c0;
    WaitTxStateMachineOk_Ptr = 0x807c4;
    PS_S4_Condition_Match_Ptr = 0x807c8;
    PS_S2_Condition_Match_Ptr = 0x807cc;
    PsCloseRF_Ptr = 0x807d0;
    PsOpenRF_Ptr = 0x807d4;
    PSModeSetting_Ptr = 0x807d8;
    Legacy_PS_Setting_Ptr = 0x807dc;
    ResetPSParm_Ptr = 0x807e0;
    Change_PS_State_Ptr = 0x807e4;
    SetPwrStateReg_Ptr = 0x807e8;
    SetSmartPSTimer_Ptr = 0x807ec;
    C2HBTInfo_Ptr = 0x807f0;
    BT_TDMA_Slot_Operation_0and3_Ptr = 0x807f4;
    FlexibleExtensionDecision_Ptr = 0x807f8;
    BTRoleChangeDefaultSetting_Ptr = 0x807fc;
    BTNullSetting_Ptr = 0x80800;
    MailboxINTHDL_Patch_Ptr = 0x80804;
    MailboxINTHDL_Ptr = 0x80808;
    BTypeTDMATimeOuthdl_Ptr = 0x8080c;
    DacSwing_Ptr = 0x80810;
    IssueBTQNull_Ptr = 0x80814;
    BTRoleChangeTBTTHDL_Ptr = 0x80818;
    BTypeTDMATBTThdl_Ptr = 0x8081c;
    BackupAntennaSetting_Ptr = 0x80820;
    C2HBTLoopback_Ptr = 0x80824;
    BTMailboxRetry_Ptr = 0x80828;
    InitBTMailbox_Ptr = 0x8082c;
    BTypeTDMABCNEarly_Ptr = 0x80830;
    InitBTypeTDMA2_Ptr = 0x80834;
    BTRoleChangeTimerHDL_Ptr = 0x80838;
    C2HBTMpRpt_Ptr = 0x8083c;
    ChangeCoexTable_Ptr = 0x80840;
    WlanActCtrl_Ptr = 0x80844;
    InitBTCoexTimer_Ptr = 0x80848;
    AOAC_ANT_SWT_Ptr = 0x8084c;
    BT_TDMA_Slot_Operation_2and5_Ptr = 0x80850;
    BT_TDMA_Slot_Operation_1and4_Ptr = 0x80854;
    FillMailbox_Ptr = 0x80858;
    WL2BTMailbox_Ptr = 0x8085c;
    Write778_Ptr = 0x80860;
    PktBufAccessCtrl_Ptr = 0x80864;
    H2CDeQueue_Ptr = 0x80868;
    H2CInQueue_Ptr = 0x8086c;
    C2HPKTRxDESC_Ptr = 0x80870;
    FillC2HContant_Ptr = 0x80874;
    IssueC2HPKT_Ptr = 0x80878;
    C2HDeQueue_Ptr = 0x8087c;
    C2HInQueue_Ptr = 0x80880;
    H2CCmdFunc_Ptr = 0x80884;
    ODM_H2C_RADebugMonitor_Ptr = 0x80888;
    ArfrRefresh_Ptr = 0x8088c;
    RateUp_search_RateMask_Ptr = 0x80890;
    check_rate_Ptr = 0x80894;
    Set_arfr_Ptr = 0x80898;
    InitialRateByRssi_Ptr = 0x8089c;
    InitRAInfo_rsvd_Ptr = 0x808a0;
    InitialRateUpdate_Ptr = 0x808a4;
    ISRSendSignalCommon_Ptr = 0x808a8;
    OSSendSignalCommon_Ptr = 0x808ac;
    pRATE_UP_FAIL_WAITING = 0x808b0;
    pARFB_table = 0x808b4;
    pRA = 0x808b8;
    pDEBUG = 0x808bc;
    pstainfo_ra = 0x808c0;
    pODM = 0x80900;
    pAOACPage1 = 0x80904;
    pAOACGlobalInfo = 0x80908;
    pNetworkListInfo = 0x8090c;
    pRWV2 = 0x80910;
    pteredo_info = 0x80914;
    pAOACReport = 0x80918;
    pSecurityInfo = 0x8091c;
    pIpv6PseudoHeaderInfo = 0x80920;
    pNDPInfo = 0x80924;
    pARPInfo = 0x8092c;
    pAOACInfo = 0x80930;
    BTcnt = 0x80934;
    BTDebugEN = 0x8095c;
    pBT_Init_Info = 0x80960;
    pBT_Page_Scan_Interval = 0x80964;
    pWIFI_Info = 0x80968;
    pBtParm = 0x8096c;
    pBTTxStatus = 0x80970;
    pBtTdmaParm = 0x80974;
    pMediaStatus = 0x80978;
    ScanEn = 0x8097c;
    pPSBTParm = 0x80980;
    pPSTParm = 0x80984;
    pPSParm = 0x80988;
    pP2PPSInfo = 0x8098c;
    pHwParm = 0x80990;
    pMichaelPktParm = 0x80994;
    pMsgKeyParm = 0x80998;
    pOpModeParm = 0x8099c;
    pDataCtrlParm = 0x809a0;
    pIpSec = 0x809a4;
    RXFF0_BNDY = 0x809a8;
    pC2HEvt = 0x809ac;
    pH2CEvt = 0x809b0;
    pRPL = 0x809b4;
    pIntHdl = 0x809b8;
    TaskBitMap = 0x809bc;
    PHYRegDef = 0x809be;
    __rom_bss_end__ = 0x809ce;
}
