Test can be run in two configurations: loopback or two chip setup.
Loopback test requires two pair of shortened pins. Two chip setup
requiers flashing nrf52 and nrf91 on nrf9160dk.

Loopback test validates basic communication using low power UART.

Two chip test validates that low power UART is resilient to interrupts
including Zero Latency Interrupts (kind of NMI interrupts). It cannot
be tested on single CPU as it requires that we trigger the scenario where
low power UART operation is interrupted on one chip while second chip
progresses with communication.

See overlay files for test setup.
