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xilskey
Vitis Drivers API Documentation
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xilskey
Vitis Drivers API Documentation
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MODIFICATION HISTORY:
Ver Who Date Changes
1.00a rpoolla 04/26/13 First release 4.00 vns 09/10/15 Added DFT control bits addresses 7.2 am 07/13/21 Fixed doxygen warnings
Macros | |
| #define | XSK_EFUSEPS_RSA_KEY_HASH_LEN_BITS (256) |
| Rsa Key hash length in bits. More... | |
| #define | XSK_EFUSEPS_RSA_HASH_LEN_ECC_CALC (260) |
| Rsa Key hash length calculation. More... | |
| #define | XSK_EFUSEPS_PRGM_STROBE_WIDTH(RefClk) ((12 * (RefClk))/1000000) |
| Strobe width calculation. More... | |
| #define | XSK_EFUSEPS_RD_STROBE_WIDTH(RefClk) ((15 * (RefClk))/100000000) |
| Modified to have max of 32 bit value. More... | |
| #define | XSK_EFUSEPS_BASE_ADDRESS (0xF800D000) |
| PSS eFUSE Register addresses. More... | |
| #define | XSK_EFUSEPS_WR_LOCK_REG_OFFSET (0x0) |
| WR_LOCK Write lock offset. More... | |
| #define | XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET (0x4) |
| WR_UNLOCK Write 0xDF0D to allow write offset. More... | |
| #define | XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET (0x8) |
| WR_LOCKSTA Write protection status offset. More... | |
| #define | XSK_EFUSEPS_CONFIG_REG_OFFSET (0xC) |
| CFG Configuration register offset. More... | |
| #define | XSK_EFUSEPS_STATUS_REG_OFFSET (0x10) |
| STATUS Status register offset. More... | |
| #define | XSK_EFUSEPS_CONTROL_REG_OFFSET (0x14) |
| CONTROL Control register offset. More... | |
| #define | XSK_EFUSEPS_PGM_STBW_REG_OFFSET (0x18) |
| PGM_STBW eFuse program strobe width register offset. More... | |
| #define | XSK_EFUSEPS_RD_STBW_REG_OFFSET (0x1C) |
| RD_STBW eFuse read strobe width register offset. More... | |
| #define | XSK_EFUSEPS_WR_LOCK_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_LOCK_REG_OFFSET) |
| WR_LOCK Write 0x767B to disallow write. More... | |
| #define | XSK_EFUSEPS_WR_UNLOCK_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET) |
| WR_UNLOCK Write 0xDF0D to allow write. More... | |
| #define | XSK_EFUSEPS_WR_LOCK_STATUS_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET) |
| WR_LOCKSTA Write protection status. More... | |
| #define | XSK_EFUSEPS_CONFIG_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_CONFIG_REG_OFFSET) |
| CFG Configuration register. More... | |
| #define | XSK_EFUSEPS_STATUS_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_STATUS_REG_OFFSET) |
| STATUS Status register. More... | |
| #define | XSK_EFUSEPS_CONTROL_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_CONTROL_REG_OFFSET) |
| CONTROL Control register. More... | |
| #define | XSK_EFUSEPS_PGM_STBW_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_PGM_STBW_REG_OFFSET) |
| PGM_STBW eFuse program strobe width register. More... | |
| #define | XSK_EFUSEPS_RD_STBW_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_RD_STBW_REG_OFFSET) |
| RD_STBW eFuse read strobe width register. More... | |
| #define | XSK_EFUSEPS_WR_LOCK_STATUS_BIT (0x1) |
| Current state of write protection mode of eFuse subsystem:- 0 Region is writable 1 Region is not writable. More... | |
| #define | XSK_EFUSEPS_CONFIG_REDUNDANCY (0x00010000) |
| Redundancy mode, if set, else single mode. More... | |
| #define | XSK_EFUSEPS_CONFIG_TSU_H_A (0x00002000) |
| eFuse read/program setup/hold control between address and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles More... | |
| #define | XSK_EFUSEPS_CONFIG_TSU_H_CS (0x00001000) |
| eFuse read/program setup/hold control between csb and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles More... | |
| #define | XSK_EFUSEPS_CONFIG_TSU_H_PS (0x00000F00) |
| eFuse program setup/hold control between ps and csb active More... | |
| #define | XSK_EFUSEPS_CONFIG_CLK_DIV (0x00000003) |
| Reference clock scaler 2 b00 bypass clock divider 2 b01 div 2 2 b10 div 4 2 h11 div 8. More... | |
| #define | XSK_EFUSEPS_STATUS_BISR_DONE (0x80000000) |
| Status Register containing BISR Controller status, trim value, and security debug info. More... | |
| #define | XSK_EFUSEPS_STATUS_BISR_GO (0x40000000) |
| Build in self test finished successfully. More... | |
| #define | XSK_EFUSEPS_STATUS_BISR_BLANK (0x00100000) |
| eFuse box is blank, i.e., not yet been written to, if set More... | |
| #define | XSK_EFUSEPS_STATUS_SDEBUG_DIS (0x00010000) |
| Security debug status, with authentication 0 security debug enabled 1 security debug disabled. More... | |
| #define | XSK_EFUSEPS_STATUS_WR_PROTECT (0x00003000) |
| eFuse write protection, if either bit is set, writes to the eFuse box are disabled More... | |
| #define | XSK_EFUSEPS_STATUS_TRIM (0x000000FC) |
| Analog trim value. More... | |
| #define | XSK_EFUSEPS_CONTROL_PS_EN (0x00000010) |
| XSK_EFUSEPS_CONTROL_REG (Control register for eFuse program, read and write control) eFuse ps control, enable programming if set. More... | |
| #define | XSK_EFUSEPS_CONTROL_WR_DIS (0x00000002) |
| eFuse write disable, if set. More... | |
| #define | XSK_EFUSEPS_CONTROL_RD_DIS (0x00000001) |
| eFuse read disable, if set More... | |
| #define | XSK_EFUSEPS_APB_START_ADDR_OFFSET (0x1000) |
| eFuse memory APB Customer key start address offset More... | |
| #define | XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET (0x20) |
| eFuse memory APB Customer key first half start address offset More... | |
| #define | XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET (0x24) |
| eFuse memory APB Customer key second half start address offset More... | |
| #define | XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET (0x28) |
| eFUSE APB address for ROM 128k CRC enable offset More... | |
| #define | XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET (0x2C) |
| eFUSE APB address for RSA authentication enable offset More... | |
| #define | XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET (0x30) |
| eFUSE DFT JTAG disable More... | |
| #define | XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET (0x34) |
| eFUSE DFT mode disable More... | |
| #define | XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET (0x5C0) |
| eFUSE APB address for RSA uart status enable on MIO48 offset More... | |
| #define | XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET (0x5C4) |
| eFUSE APB address for non-secure INIT_B signaling offset More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET (0x80) |
| eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled) More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET (0x580) |
| eFuse memory APB Customer key first half end address More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET (0x880) |
| If Single mode is enabled both First and Second half addresses are valid. More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET (0xE00) |
| eFuse memory APB Customer key second half end address More... | |
| #define | XSK_EFUSEPS_APB_MIRROR_ADDRESS(Addr) (Addr + 0x87C - (2*(Addr%128))) |
| Mirror Address = addr + 2nd half start address + mirror offset. More... | |
| #define | XSK_EFUSEPS_APB_START_ADDR (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_APB_START_ADDR_OFFSET) |
| eFuse memory APB start address More... | |
| #define | XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET) |
| eFuse memory APB Customer key second half start address More... | |
| #define | XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET) |
| eFuse memory APB Customer key second half start address More... | |
| #define | XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET) |
| eFUSE APB address for ROM 128k CRC enable More... | |
| #define | XSK_EFUSEPS_APB_RSA_AUTH_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET) |
| eFUSE APB address for RSA authentication enable More... | |
| #define | XSK_EFUSEPS_APB_DFT_JTAG_DISABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET) |
| eFuse DFT JTAG disable More... | |
| #define | XSK_EFUSEPS_APB_DFT_MODE_DISABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET) |
| eFuse DFT mode disable More... | |
| #define | XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET) |
| eFUSE APB address for RSA uart status enable on MIO48 More... | |
| #define | XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET) |
| eFUSE APB address for non-secure INIT_B signaling More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET) |
| eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled) More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET) |
| eFuse memory APB Customer key first half end address More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET) |
| If Single mode is enabled both First and Second half addresses are valid. More... | |
| #define | XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET) |
| eFuse memory APB Customer key second half end address More... | |
| #define | XSK_EFUSEPS_APB_MIRROR_ADDRESS(Addr) (Addr + 0x87C - (2*(Addr%128))) |
| Mirror Address = addr + 2nd half start address + mirror offset. More... | |
| #define | XSK_EFUSEPS_CONTROLER_LOCK() Xil_Out32(XSK_EFUSEPS_WR_LOCK_REG,0x767B) |
| This macro is used to lock the efuse controller. More... | |
| #define | XSK_EFUSEPS_CONTROLER_UNLOCK() Xil_Out32(XSK_EFUSEPS_WR_UNLOCK_REG,0xDF0D) |
| This macro is used to unlock the efuse controller. More... | |
| #define | XSK_EFUSEPS_CONTROLER_LOCK_STATUS() (Xil_In32(XSK_EFUSEPS_WR_LOCK_STATUS_REG) & 0x1) |
| This macro is used to check the status whether eFuse controller is locked or not. More... | |
| #define | XSK_EFUSEPS_CONTROLER_OP_MODE() ((Xil_In32(XSK_EFUSEPS_CONFIG_REG) & XSK_EFUSEPS_CONFIG_REDUNDANCY)? 1 : 0) |
| This macro is used to determine operation mode of efuse controller. More... | |
| #define | XilSKey_EfusePs_IsEfuseWriteProtected() ((Xil_In32(XSK_EFUSEPS_STATUS_REG) & XSK_EFUSEPS_STATUS_WR_PROTECT)? TRUE : FALSE) |
| This macro is used to check whether eFuse is write protected or not. More... | |
Hamming information | |
| #define | XSK_EFUSEPS_HAMMING_LOOPS (10) |
| < Hamming loops, data and length More... | |
| #define | XSK_EFUSEPS_HAMMING_LENGTH (31) |
| #define | XSK_EFUSEPS_HAMMING_DATA (26) |
Mode types | |
| #define | XSK_EFUSEPS_SINGLE_MODE (0x0) |
| < Mode types and definitions More... | |
| #define | XSK_EFUSEPS_REDUNDANCY_MODE (0x1) |
ReadMode | |
| #define | XSK_EFUSEPS_READ_MODE_NORMAL (0x1) |
| < ReadModes and definitions More... | |
| #define | XSK_EFUSEPS_READ_MODE_MARGIN_1 (0x2) |
| #define | XSK_EFUSEPS_READ_MODE_MARGIN_2 (0x3) |
EFUSE operation modes | |
| #define | XSK_EFUSEPS_ENABLE_PROGRAMMING (0x1) |
| < EFUSE operation modes and definitions More... | |
| #define | XSK_EFUSEPS_ENABLE_READ (0x2) |
| #define | XSK_EFUSEPS_ENABLE_WRITE (0x4) |
EFUSE Reference Clock frequency | |
| #define | XSK_EFUSEPS_REFCLK_LOW_FREQ (20000000) |
| < EFUSE Reference Clock frequency definitions More... | |
| #define | XSK_EFUSEPS_REFCLK_HIGH_FREQ (60000000) |
eFuse read margin control | |
| #define | XSK_EFUSEPS_CONFIG_MARGIN_RD (0x00000030) |
| < eFuse read margin control: 00 normal, 01 margin 1, 10 margin 2, 11 - undefined More... | |
| #define | XSK_EFUSEPS_CONFIG_RD_NORMAL (0x00000000) |
| #define | XSK_EFUSEPS_CONFIG_RD_MARGIN_1 (0x00000010) |
| #define | XSK_EFUSEPS_CONFIG_RD_MARGIN_2 (0x00000020) |
Xilinx reserved Tests bits registers | |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET (0x80) |
| < Xilinx reserved Tests bits in the First half of the eFUSE block offsets and definitions More... | |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41_OFFSET (0x104) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62_OFFSET (0x188) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83_OFFSET (0x20C) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4_OFFSET (0x290) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5_OFFSET (0x314) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6_OFFSET (0x398) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107_OFFSET (0x41C) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128_OFFSET (0x4A0) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149_OFFSET (0x524) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET (0x8FC) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E_OFFSET (0x978) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D_OFFSET (0x9F4) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C_OFFSET (0xA70) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB_OFFSET (0xAEC) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA_OFFSET (0xB68) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9_OFFSET (0xBE4) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318_OFFSET (0xC60) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337_OFFSET (0xCDC) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356_OFFSET (0xD58) |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_OFFSET (0x1C) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_OFFSET (0x40) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_OFFSET (0x7C) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_OFFSET (0x600) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_OFFSET (0x7FC) |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET (0x860) |
| < Xilinx reserved Tests bits in the Second half of the eFUSE block offsets More... | |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF_OFFSET (0x87C) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF_OFFSET (0x800) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF_OFFSET (0x83C) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF_OFFSET (0xE00) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF_OFFSET (0xFFC) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET) |
| < Xilinx reserved Tests bits in the First half of the eFUSE block address More... | |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET) |
| < Xilinx reserved Tests bits in the First half of the eFUSE block address More... | |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356_OFFSET) |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR) |
| < Xilinx reserved Tests bits in the First half of the eFUSE block address More... | |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_OFFSET) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_OFFSET) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_OFFSET) |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET) |
| < Xilinx reserved Tests bits in the Second half of the eFUSE block address More... | |
| #define | XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF_OFFSET) |
| #define | XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF_OFFSET) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF_OFFSET) |
| #define | XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF_OFFSET) |
Functions | |
| void | XilSKey_EfusePs_GenerateMatrixMap (void) |
| This function is used to generate the matrix map of the G and H for hamming code (31,26). More... | |
| u8 | XilSKey_EfusePs_EccDecode (const u8 *Corrupt, u8 *Syndrome) |
| This function is used to decode the incoming encoded byte. More... | |
| void | XilSKey_EfusePs_EccEncode (const u8 *InData, u8 *Ecc) |
| This function is used to encode the incoming data byte. More... | |
| u32 | XilSKey_EfusePs_ControllerConfig (u8 CtrlMode, u32 RefClk, u8 ReadMode) |
| This function is used to set the controller mode, read mode along with the read and program strobe width values based on the reference clock. More... | |
| u8 | XilSKey_EfusePs_IsAddressXilRestricted (u32 Addr) |
| This function is used to check whether eFuse bit is xilinx reserved bit or not. More... | |
| void | XilSKey_EfusePs_ControllerSetReadWriteEnable (u32 ReadWriteEnable) |
| This function is used to enable the read/write/program the eFUSE array. More... | |
| u32 | XilSKey_EfusePs_ReadEfuseBit (u32 Addr, u8 *Data) |
| This function is used to read the eFuse bit value. More... | |
| u32 | XilSKey_EfusePs_WriteEfuseBit (u32 Addr) |
| This function is used to program the eFuse bit value. More... | |
| #define XilSKey_EfusePs_IsEfuseWriteProtected | ( | ) | ((Xil_In32(XSK_EFUSEPS_STATUS_REG) & XSK_EFUSEPS_STATUS_WR_PROTECT)? TRUE : FALSE) |
This macro is used to check whether eFuse is write protected or not.
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET) |
eFuse memory APB Customer key first half end address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET (0x580) |
eFuse memory APB Customer key first half end address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET) |
eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled)
If Redundant mode is enabled only First half addresses are valid.
eFuse memory APB Customer key first half start address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET (0x80) |
eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled)
If Redundant mode is enabled only First half addresses are valid. eFuse memory APB Customer key first half start address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET) |
eFuse memory APB Customer key second half end address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET (0xE00) |
eFuse memory APB Customer key second half end address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET) |
If Single mode is enabled both First and Second half addresses are valid.
eFuse memory APB Customer key second half start address
| #define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET (0x880) |
If Single mode is enabled both First and Second half addresses are valid.
eFuse memory APB Customer key second half start address
| #define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET) |
eFuse DFT JTAG disable
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET (0x30) |
eFUSE DFT JTAG disable
| #define XSK_EFUSEPS_APB_DFT_MODE_DISABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET) |
eFuse DFT mode disable
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET (0x34) |
eFUSE DFT mode disable
| #define XSK_EFUSEPS_APB_MIRROR_ADDRESS | ( | Addr | ) | (Addr + 0x87C - (2*(Addr%128))) |
Mirror Address = addr + 2nd half start address + mirror offset.
| #define XSK_EFUSEPS_APB_MIRROR_ADDRESS | ( | Addr | ) | (Addr + 0x87C - (2*(Addr%128))) |
Mirror Address = addr + 2nd half start address + mirror offset.
| #define XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET) |
eFUSE APB address for ROM 128k CRC enable
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET (0x28) |
eFUSE APB address for ROM 128k CRC enable offset
| #define XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET) |
eFUSE APB address for non-secure INIT_B signaling
| #define XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET (0x5C4) |
eFUSE APB address for non-secure INIT_B signaling offset
| #define XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET) |
eFUSE APB address for RSA uart status enable on MIO48
| #define XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET (0x5C0) |
eFUSE APB address for RSA uart status enable on MIO48 offset
| #define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET) |
eFUSE APB address for RSA authentication enable
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET (0x2C) |
eFUSE APB address for RSA authentication enable offset
| #define XSK_EFUSEPS_APB_START_ADDR (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_APB_START_ADDR_OFFSET) |
eFuse memory APB start address
| #define XSK_EFUSEPS_APB_START_ADDR_OFFSET (0x1000) |
eFuse memory APB Customer key start address offset
| #define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR) |
< Xilinx reserved Tests bits in the First half of the eFUSE block address
Referenced by XilSKey_EfusePs_IsAddressXilRestricted().
| #define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET) |
< Xilinx reserved Tests bits in the Second half of the eFUSE block address
Referenced by XilSKey_EfusePs_IsAddressXilRestricted().
| #define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET (0x860) |
< Xilinx reserved Tests bits in the Second half of the eFUSE block offsets
| #define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET) |
eFuse memory APB Customer key second half start address
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET (0x20) |
eFuse memory APB Customer key first half start address offset
| #define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET) |
eFuse memory APB Customer key second half start address
Referenced by XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET (0x24) |
eFuse memory APB Customer key second half start address offset
| #define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET) |
< Xilinx reserved Tests bits in the First half of the eFUSE block address
Referenced by XilSKey_EfusePs_IsAddressXilRestricted().
| #define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET (0x80) |
< Xilinx reserved Tests bits in the First half of the eFUSE block offsets and definitions
| #define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET) |
< Xilinx reserved Tests bits in the First half of the eFUSE block address
Referenced by XilSKey_EfusePs_IsAddressXilRestricted().
| #define XSK_EFUSEPS_BASE_ADDRESS (0xF800D000) |
PSS eFUSE Register addresses.
eFuse base address
| #define XSK_EFUSEPS_CONFIG_CLK_DIV (0x00000003) |
Reference clock scaler 2 b00 bypass clock divider 2 b01 div 2 2 b10 div 4 2 h11 div 8.
XSK_EFUSEPS_STATUS_REG (Status Register)
| #define XSK_EFUSEPS_CONFIG_MARGIN_RD (0x00000030) |
< eFuse read margin control: 00 normal, 01 margin 1, 10 margin 2, 11 - undefined
| #define XSK_EFUSEPS_CONFIG_REDUNDANCY (0x00010000) |
Redundancy mode, if set, else single mode.
This bit only applies to APB access. BISR and eFuse reader always work in redundancy mode.
| #define XSK_EFUSEPS_CONFIG_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_CONFIG_REG_OFFSET) |
CFG Configuration register.
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_CONFIG_REG_OFFSET (0xC) |
CFG Configuration register offset.
| #define XSK_EFUSEPS_CONFIG_TSU_H_A (0x00002000) |
eFuse read/program setup/hold control between address and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_CONFIG_TSU_H_CS (0x00001000) |
eFuse read/program setup/hold control between csb and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles
| #define XSK_EFUSEPS_CONFIG_TSU_H_PS (0x00000F00) |
eFuse program setup/hold control between ps and csb active
| #define XSK_EFUSEPS_CONTROL_PS_EN (0x00000010) |
XSK_EFUSEPS_CONTROL_REG (Control register for eFuse program, read and write control) eFuse ps control, enable programming if set.
Referenced by XilSKey_EfusePs_ControllerSetReadWriteEnable().
| #define XSK_EFUSEPS_CONTROL_RD_DIS (0x00000001) |
eFuse read disable, if set
Referenced by XilSKey_EfusePs_ControllerSetReadWriteEnable().
| #define XSK_EFUSEPS_CONTROL_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_CONTROL_REG_OFFSET) |
CONTROL Control register.
Referenced by XilSKey_EfusePs_ControllerSetReadWriteEnable().
| #define XSK_EFUSEPS_CONTROL_REG_OFFSET (0x14) |
CONTROL Control register offset.
| #define XSK_EFUSEPS_CONTROL_WR_DIS (0x00000002) |
eFuse write disable, if set.
Referenced by XilSKey_EfusePs_ControllerSetReadWriteEnable().
| #define XSK_EFUSEPS_CONTROLER_LOCK | ( | ) | Xil_Out32(XSK_EFUSEPS_WR_LOCK_REG,0x767B) |
This macro is used to lock the efuse controller.
Referenced by XilSKey_EfusePs_Read(), and XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_CONTROLER_LOCK_STATUS | ( | ) | (Xil_In32(XSK_EFUSEPS_WR_LOCK_STATUS_REG) & 0x1) |
This macro is used to check the status whether eFuse controller is locked or not.
Referenced by XilSKey_EfusePs_Read(), XilSKey_EfusePs_ReadStatus(), and XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_CONTROLER_OP_MODE | ( | ) | ((Xil_In32(XSK_EFUSEPS_CONFIG_REG) & XSK_EFUSEPS_CONFIG_REDUNDANCY)? 1 : 0) |
This macro is used to determine operation mode of efuse controller.
| #define XSK_EFUSEPS_CONTROLER_UNLOCK | ( | ) | Xil_Out32(XSK_EFUSEPS_WR_UNLOCK_REG,0xDF0D) |
This macro is used to unlock the efuse controller.
Referenced by XilSKey_EfusePs_Read(), XilSKey_EfusePs_ReadStatus(), and XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_ENABLE_PROGRAMMING (0x1) |
< EFUSE operation modes and definitions
Referenced by XilSKey_EfusePs_ControllerSetReadWriteEnable(), and XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_HAMMING_LOOPS (10) |
< Hamming loops, data and length
| #define XSK_EFUSEPS_PGM_STBW_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_PGM_STBW_REG_OFFSET) |
PGM_STBW eFuse program strobe width register.
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_PGM_STBW_REG_OFFSET (0x18) |
PGM_STBW eFuse program strobe width register offset.
| #define XSK_EFUSEPS_PRGM_STROBE_WIDTH | ( | RefClk | ) | ((12 * (RefClk))/1000000) |
Strobe width calculation.
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_RD_STBW_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_RD_STBW_REG_OFFSET) |
RD_STBW eFuse read strobe width register.
PSS eFUSE register bit defines & description XSK_EFUSEPS_WR_LOCK_STATUS_REG (Write Protection Status Register)
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_RD_STBW_REG_OFFSET (0x1C) |
RD_STBW eFuse read strobe width register offset.
| #define XSK_EFUSEPS_RD_STROBE_WIDTH | ( | RefClk | ) | ((15 * (RefClk))/100000000) |
Modified to have max of 32 bit value.
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_READ_MODE_NORMAL (0x1) |
< ReadModes and definitions
Referenced by XilSKey_EfusePs_Read(), and XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_REFCLK_LOW_FREQ (20000000) |
< EFUSE Reference Clock frequency definitions
Referenced by XilSKey_EfusePs_ControllerConfig().
| #define XSK_EFUSEPS_RSA_HASH_LEN_ECC_CALC (260) |
Rsa Key hash length calculation.
| #define XSK_EFUSEPS_RSA_KEY_HASH_LEN_BITS (256) |
Rsa Key hash length in bits.
| #define XSK_EFUSEPS_SINGLE_MODE (0x0) |
< Mode types and definitions
Referenced by XilSKey_EfusePs_ControllerConfig(), and XilSKey_EfusePs_Write().
| #define XSK_EFUSEPS_STATUS_BISR_BLANK (0x00100000) |
eFuse box is blank, i.e., not yet been written to, if set
| #define XSK_EFUSEPS_STATUS_BISR_DONE (0x80000000) |
Status Register containing BISR Controller status, trim value, and security debug info.
Build in self test finished at boot time
| #define XSK_EFUSEPS_STATUS_BISR_GO (0x40000000) |
Build in self test finished successfully.
| #define XSK_EFUSEPS_STATUS_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_STATUS_REG_OFFSET) |
STATUS Status register.
Referenced by XilSKey_EfusePs_ReadStatus().
| #define XSK_EFUSEPS_STATUS_REG_OFFSET (0x10) |
STATUS Status register offset.
| #define XSK_EFUSEPS_STATUS_SDEBUG_DIS (0x00010000) |
Security debug status, with authentication 0 security debug enabled 1 security debug disabled.
| #define XSK_EFUSEPS_STATUS_TRIM (0x000000FC) |
Analog trim value.
| #define XSK_EFUSEPS_STATUS_WR_PROTECT (0x00003000) |
eFuse write protection, if either bit is set, writes to the eFuse box are disabled
| #define XSK_EFUSEPS_WR_LOCK_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_LOCK_REG_OFFSET) |
WR_LOCK Write 0x767B to disallow write.
| #define XSK_EFUSEPS_WR_LOCK_REG_OFFSET (0x0) |
WR_LOCK Write lock offset.
| #define XSK_EFUSEPS_WR_LOCK_STATUS_BIT (0x1) |
Current state of write protection mode of eFuse subsystem:- 0 Region is writable 1 Region is not writable.
Any attempted writes are ignored, but reads will complete as normal.XSK_EFUSEPS_CONFIG_REG (Configuration Register)
| #define XSK_EFUSEPS_WR_LOCK_STATUS_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET) |
WR_LOCKSTA Write protection status.
| #define XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET (0x8) |
WR_LOCKSTA Write protection status offset.
| #define XSK_EFUSEPS_WR_UNLOCK_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET) |
WR_UNLOCK Write 0xDF0D to allow write.
| #define XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET (0x4) |
WR_UNLOCK Write 0xDF0D to allow write offset.
| u32 XilSKey_EfusePs_ControllerConfig | ( | u8 | CtrlMode, |
| u32 | RefClk, | ||
| u8 | ReadMode | ||
| ) |
This function is used to set the controller mode, read mode along with the read and program strobe width values based on the reference clock.
| CtrlMode | is the mode of the controller
|
| RefClk | is the CPU 1x reference clock frequency. Clock frequency can be between 20MHz to 100MHz specified in Hz |
| ReadMode | is the read mode of the controller
|
Test Cases: Check single mode in CFG Reg Check redundancy mode in CFG Reg Check strobe width values for write mode Check strobe width values for various read mode Check Normal Read mode setting in CFG Reg Check Margin 1 Read mode setting in CFG Reg Check Margin 2 Read mode setting in CFG Reg Boundary Conditions
Check the parameters Mode can be Single or Redundancy mode
Ref Clock should be between 20MHz - 60MHz
3 read modes are supported
Set the controller mode
Set the controller read mode
Program the Strobe width values for read and write 12us is required for write and 150ns is required for read PGM_STBW = ceiling(12us/ref_clk period) RD_STBW = ceiling(150ns/ref_clk period)
References XSK_EFUSEPS_CONFIG_REG, XSK_EFUSEPS_CONFIG_TSU_H_A, XSK_EFUSEPS_ERROR_CONTROLLER_MODE, XSK_EFUSEPS_ERROR_READ_MODE, XSK_EFUSEPS_ERROR_REF_CLOCK, XSK_EFUSEPS_PGM_STBW_REG, XSK_EFUSEPS_PRGM_STROBE_WIDTH, XSK_EFUSEPS_RD_STBW_REG, XSK_EFUSEPS_RD_STROBE_WIDTH, XSK_EFUSEPS_REFCLK_LOW_FREQ, and XSK_EFUSEPS_SINGLE_MODE.
Referenced by XilSKey_EfusePs_Read(), and XilSKey_EfusePs_Write().
| void XilSKey_EfusePs_ControllerSetReadWriteEnable | ( | u32 | ReadWriteEnable | ) |
This function is used to enable the read/write/program the eFUSE array.
| ReadWriteEnable | 0x1 - Enable programming 0x2 - Enable read 0x4 - Enable write |
Test Cases
Reset the values Disable programming Disable reading Disable writing
References XSK_EFUSEPS_CONTROL_PS_EN, XSK_EFUSEPS_CONTROL_RD_DIS, XSK_EFUSEPS_CONTROL_REG, XSK_EFUSEPS_CONTROL_WR_DIS, and XSK_EFUSEPS_ENABLE_PROGRAMMING.
Referenced by XilSKey_EfusePs_Read(), and XilSKey_EfusePs_Write().
| u8 XilSKey_EfusePs_EccDecode | ( | const u8 * | Corrupt, |
| u8 * | Syndrome | ||
| ) |
This function is used to decode the incoming encoded byte.
| Corrupt | is the input encoded data. It has 26 bit data with 5 bit parity data |
| Syndrome | is the output updated with the parity error information. |
TDD Cases: Check the parameters Check the decode with out any error Check the decode with 1 bit error Check the decode with 2 bit error Check the decode for boundary cases Check for memory corruption
References ErrorCodeIndex, and Matrix.
| void XilSKey_EfusePs_EccEncode | ( | const u8 * | InData, |
| u8 * | Ecc | ||
| ) |
This function is used to encode the incoming data byte.
It uses hamming (31,26) algorithm. 26 bits are encoded to 31 bits
| InData | is 26 bit input data with each bit represented in one byte |
| Ecc | is the 31 bit encoded data with each bit represented in one byte |
TDD Cases: Check the parameters Check the encoded data for different input data Check the input data for boundary cases Check for memory corruption
References Matrix.
| void XilSKey_EfusePs_GenerateMatrixMap | ( | void | ) |
This function is used to generate the matrix map of the G and H for hamming code (31,26).
G is [31,5] and defined as [A|I], I is identity matrix of [5,5].
TDD Cases: Check the generated matrix Check the memory corruption of the generated matrix
References ErrorCodeIndex, and Matrix.
| u8 XilSKey_EfusePs_IsAddressXilRestricted | ( | u32 | Addr | ) |
This function is used to check whether eFuse bit is xilinx reserved bit or not.
| Addr | is the address of the eFuse bit. |
Test Cases: with different address values Boundary values for addr
Check for xilinx test bits
Check for xilinx reserved bits
References XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR, XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF, XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20, and XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F.
Referenced by XilSKey_EfusePs_ReadEfuseBit(), and XilSKey_EfusePs_WriteEfuseBit().
| u32 XilSKey_EfusePs_ReadEfuseBit | ( | u32 | Addr, |
| u8 * | Data | ||
| ) |
This function is used to read the eFuse bit value.
Before using this function set the controller mode and read mode as required. Also, strobe width values are to be set properly based on the reference clock for successful reading
| Addr | is the address of the eFuse bit. |
| Data | has the read eFuse value stored in it. |
Test Cases Read in Single mode Read in redundancy mode Read for restricted address Boundary Checks for address
References XilSKey_EfusePs_IsAddressXilRestricted(), and XSK_EFUSEPS_ERROR_ADDRESS_XIL_RESTRICTED.
| u32 XilSKey_EfusePs_WriteEfuseBit | ( | u32 | Addr | ) |
This function is used to program the eFuse bit value.
Before using this function set the controller mode and read mode as required. Also, strobe width values are to be set properly based on the reference clock for successful programming
| Addr | is the address of the eFuse bit. |
Test Cases Write in Single mode Write in redundancy mode Write for restricted address Boundary Checks for address Strobe width are not proper (Check if it makes sense)
Check if Address is restricted
Send success when bit is already programmed
Providing 15us delay Timer takes 100ns as slice. 15us = 150 * 100ns
References XilSKey_Efuse_IsTimerExpired(), XilSKey_Efuse_SetTimeOut(), XilSKey_EfusePs_IsAddressXilRestricted(), and XSK_EFUSEPS_ERROR_ADDRESS_XIL_RESTRICTED.