Overview

Note

                    Contains the function definitions for the PL eFUSE functionality.

MODIFICATION HISTORY:

Ver Who Date Changes

1.00a rpoolla 04/26/13 First release 1.02a hk 10/28/13 Added API's to read status bits and key.PR# 735957 2.00 hk 22/01/14 Corrected PL voltage checks to VCCINT and VCCAUX. CR#768077 2.1 kvn 04/01/15 Fixed warnings. CR#716453. 3.00 vns 31/07/15 Added efuse functionality for Ultrascale. 4.0 vns 10/01/15 provided conditional compilation to support ZynqMp platform also. Corrected error code names of Ultrascale efuse PL 5.0 vns 07/01/16 Verificaion of programming bits is done by performing all Margin reads. Added conditions for programming control and secure bits. 6.00 vns 29/06/16 Added Margin 2 read verification after programming every Zynq's eFUSE PL bit CR #953052. 07/07/16 Modified XilSKey_EfusePl_ProgramBit_Ultra such that it returns error code when JtagWrite_Ultrascale fails programming eFUSE bit. Error occurs only when Hardware Module has encountered timeout. 26/07/16 Added 128 bit user key programming and reading. Provided single bit programming feature for 32 and 128 bit user keys for eFUSE Ultrascale. 6.4 vns 02/27/18 Added support for programming secure bit 6 - enable obfuscation feature for eFUSE AES key 6.6 vns 06/06/18 Added doxygen tags 6.7 psl 03/20/19 Added eFuse key write support for SSIT devices. arc 04/04/19 Fixed CPP warnings. psl 04/15/19 Added JtagServerInit function. 6.8 psl 05/21/19 Added else case to clear UserFuses_TobePrgrmd psl 08/23/19 Added Debug define to avoid writing of eFuse. vns 08/29/19 Initialized Status variables 6.9 vns 03/18/20 Fixed Armcc compilation errors 7.2 am 07/13/21 Fixed doxygen warnings 7.3 har 11/15/21 Removed local variable ErrorCode in XilSKey_EfusePl_GetRowData_Ultra()

Macros
#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_ROW (0)
	Fuse Ctrl Row. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_AES_KEY_SIZE (256)
	AES Key size. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_USER_KEY_SIZE (32)
	32 bit User key size More...

#define	XSK_EFUSEPL_ARRAY_FUSE_128BIT_USER_SIZE (128)
	128 bit User key size More...

#define	XSK_EFUSEPL_ARRAY_MAX_ROW (32)
	PLeFUSE Max Rows. More...

#define	XSK_EFUSEPL_ARRAY_MAX_COL (32)
	PLeFUSE Max Columns. More...

#define	XSK_EFUSEPL_ARRAY_AES_DATA_ROW_START (20)
	AES Data Start Row. More...

#define	XSK_EFUSEPL_ARRAY_AES_DATA_ROW_END (30)
	AES Data End Row. More...

#define	XSK_EFUSEPL_ARRAY_USER_DATA_START_ROW (31)
	User Data Start Row. More...

#define	XSK_EFUSEPL_ARRAY_AES_DATA_BITS_IN_30th_ROW (16)
	AES Data bits count in 30th Row. More...

#define	XSK_EFUSEPL_ARRAY_MAX_COL_ULTRA_PLUS (16)
	Ultrascale plus max bits in a row. More...

#define	XSK_EFUSEPL_ARRAY_USER_DATA_BITS_IN_30th_ROW (8)
	User Data bits count in 30th Row. More...

#define	XSK_EFUSEPL_ARRAY_MAX_PAYLAOD_BITS_IN_A_ROW (24)
	Max Pay load in Row. More...

#define	XSK_EFUSEPL_ARRAY_MAX_ECC_BITS_IN_A_ROW (6)
	Max ECC bits in a Row. More...

#define	XSK_EFUSEPL_ARRAY_ECC_START_BIT_IN_A_ROW (24)
	ECC Start Bit position in a Row. More...

#define	XSK_EFUSEPL_ARRAY_ECC_END_BIT_IN_A_ROW (29)
	ECC End Bit position in a Row. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_MAX_BITS (11)
	Fuse Control max bits. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_INDEX (14)
	Redundant bit Index. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_START_BIT (0)
	Fuse Control Start bit. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_END_BIT (10)
	Fuse Control Start bit. More...

#define	XSK_EFUSEPL_ARRAY_UNSUPPORTED_BIT6 (6)
	Unsupported bit. More...

#define	XSK_EFUSEPL_ARRAY_UNSUPPORTED_BIT7 (7)
	Unsupporte bit. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_START_BIT (14)
	Redundant bit start Index. More...

#define	XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT6 (20)
	Unsupported bit. More...

#define	XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT7 (21)
	Unsupported bit. More...

#define	XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_END_BIT (24)
	Redundant bit End Index. More...

#define	XSK_EFUSEPL_MAX_REF_CLK_FREQ 60000000
	Max Ref Clk Frequency. More...

#define	XSK_EFUSEPL_MIN_REF_CLK_FREQ 20000000
	Min Ref Clk Frequency. More...

#define	XSK_EFUSEPL_CNTRL_ROW_ULTRA (1)
	Control row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_DNA_ROW_ULTRA (7)
	DNA row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_AES_ROW_START_ULTRA (20)
	AES key start row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_AES_ROW_END_ULTRA (27)
	AES key end row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_USER_ROW_ULTRA (28)
	USER key start row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_SEC_ROW_ULTRA (10)
	Secure row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_RSA_ROW_START_ULTRA (12)
	RSA start row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_RSA_ROW_END_ULTRA (23)
	RSA end row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA (0)
	128 bit USER key start row of FUSE for Ultrascale series More...

#define	XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA (3)
	128 bit USER key end row of FUSE for Ultrascale series More...

#define	XSK_EFUSEPL_DNA_KEY_SIZE_ULTRA (96)
	DNA key size of Ultrascale series. More...

#define	XSK_EFUSEPL_RSA_HASH_SIZE_ULTRA (384)
	RSA hash size of Ultrascale series. More...

#define	XSK_EFUSEPL_SEC_MAX_BITS_ULTRA (7)
	Secure row max bits of Ultrascale series. More...

#define	XSK_EFUSEPL_CNTRL_MAX_BITS_ULTRA (17)
	Fuse Control max bits of Ultrascale series. More...

#define	XSK_EFUSEPL_MAX_BITS_IN_A_ROW_ULTRA (32)
	Max Pay load in Row. More...

#define	XSK_EFUSEPL_END_BIT_IN_A_ROW_ULTRA (31)
	FUSE end bit in a row of Ultrascale series. More...

#define	XSK_EFUSEPL_CTRL_ROW_END_BIT_ULTRA (16)
	Control row end bit of Ultrascale series. More...

#define	XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA (6)
	Secure row end bit of Ultrascale series. More...

#define	XSK_EFUSEPL_CNTRL_ROW_START_ULTRA_PLUS (2)
	Control row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_CNTRL_ROW_END_ULTRA_PLUS (3)
	Control row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_DNA_ROW_START_ULTRA_PLUS (0)
	DNA row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_DNA_ROW_END_ULTRA_PLUS (5)
	DNA row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_AES_ROW_START_ULTRA_PLUS (5)
	AES key start row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_AES_ROW_END_ULTRA_PLUS (20)
	AES key end row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_USER_ROW_START_ULTRA_PLUS (30)
	USER key start row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_USER_ROW_END_ULTRA_PLUS (31)
	USER key start row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_SEC_ROW_ULTRA_PLUS (4)
	Secure row of FUSE for Ultrascale series. More...

#define	XSK_EFUSEPL_RSA_ROW_START_ULTRA_PLUS (6)
	RSA start row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_RSA_ROW_END_ULTRA_PLUS (29)
	RSA end row of FUSE for Ultrascale plus series. More...

#define	XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA_PLUS (21)
	128 bit USER key start row of FUSE for Ultrascale plus series More...

#define	XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA_PLUS (28)
	128 bit USER key end row of FUSE for Ultrascale plus series More...

#define	XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT3_ULTRA (3)
	Unsupported bits of Control register. More...

#define	XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT4_ULTRA (4)
	< Unsupported bit in ctrl register More...

#define	XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_START_ULTRA (10)
	< Unsupported bit in ctrl register More...

#define	XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_END_ULTRA (14)
	< Unsupported bit in ctrl register More...

#define	XSK_EFUSEPL_MAX_REF_CLK_FREQ 60000000
	Max Ref Clk Frequency. More...

#define	XSK_EFUSEPL_MIN_REF_CLK_FREQ 20000000
	Min Ref Clk Frequency. More...

#define	XSK_EFUSEPL_PAGE_0_ULTRA (0)
	Page 0 for Ultrascale series. More...

#define	XSK_EFUSEPL_PAGE_1_ULTRA (1)
	Page 1 for Ultrascale series. More...

#define	XSK_EFUSEPL_REDUNDANT_ULTRA (1)
	Redundant read selection for Ultrascale series. More...

#define	XSK_EFUSEPL_NORMAL_ULTRA (0)
	Normal read selection for Ultrascale series. More...

Enumerations
enum	XSK_EfusePl_MarginOption { XSK_EFUSEPL_READ_NORMAL = 0x1, XSK_EFUSEPL_READ_MARGIN_1 = 0x2, XSK_EFUSEPL_READ_MARGIN_2 = 0x4, XSK_EFUSEPL_READ_MARGIN_MAX = 0x7 }
	Read or Write eFUSE Margin Options. More...

enum	XSKEfusePl_FuseCntrlBits { XSK_EFUSEPL_CNTRL_FORCE_PCYCLE_RECONFIG = 0x01, XSK_EFUSEPL_CNTRL_DISABLE_KEY_WRITE, XSK_EFUSEPL_CNTRL_DISABLE_AES_KEY_READ, XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_READ, XSK_EFUSEPL_CNTRL_DISABLE_FUSE_CNTRL_WRITE, XSK_EFUSEPL_CNTRL_FORCE_USE_AES_ONLY = 0x08, XSK_EFUSEPL_CNTRL_JTAG_CHAIN_DISABLE, XSK_EFUSEPL_CNTRL_BBRAM_KEY_DISABLE }
	Fuse Control Row Bit Indices. More...

enum	XSKEfusePl_FuseCntrlBits_Ultra { XSK_EFUSEPL_CNTRL_DISABLE_KEY_RD_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_RD_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_SEC_RD_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_CNTRL_WR_ULTRA = 5, XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_RD_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_KEY_WR_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_WR_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_SEC_WR_ULTRA, XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_WR_ULTRA = 15, XSK_EFUSEPL_CNTRL_DISABLE_128BIT_USR_KEY_WR_ULTRA }
	Fuse Control Row Bit Indices of Ultrascale series. More...

enum	XSKEfusePl_FuseSecureBits_Ultra { XSK_EFUSEPL_SEC_ALLOW_ENCRYPT_ONLY, XSK_EFUSEPL_SEC_FORCE_AES_ONLY_ULTRA, XSK_EFUSEPL_SEC_RSA_AUTH_EN_ULTRA, XSK_EFUSEPL_SEC_JTAG_CHAIN_DISABLE_ULTRA, XSK_EFUSEPL_SEC_DISABLE_INTRNL_TEST_ACCESS_ULTRA, XSK_EFUSEPL_SEC_DISABLE_DECRPTR_ULTRA, XSK_EFUSEPL_SEC_ENABLE_OBFUSCATION_ULTRA }
	Fuse Secure Row Bit Indices of Ultrascale series. More...

Functions
int	JtagServerInit (XilSKey_EPl *PlInstancePtr)
	JTAG Server Initialization routine. More...

void	JtagWrite (unsigned char row, unsigned char bit)
	JTAG Server Write routine. More...

void	JtagRead (unsigned char row, unsigned int *row_data, unsigned char marginOption)
	JTAG Server Read routine. More...

int	JtagWrite_Ultrascale (u8 Row, u8 Bit, u8 Page, u8 Redundant)
	This function blows the fuse of Ultrascale with provided parameters. More...

void	JtagRead_Ultrascale (u8 Row, u32 *RowData, u8 MarginOption, u8 Page, u8 Redundant)
	This function reads entire row of Ultrascale's EFUSE. More...

void	JtagRead_Status_Ultrascale (u32 *Rowdata)
	This function reads the status row of Ultrascale's EFUSE and updates the pointer. More...

u32	JtagAES_Check_Ultrascale (u32 *Crc, u8 MarginOption)
	This function verifies the AES key of Ultrascale's EFUSE with provided CRC value. More...

u32	XilSKey_EfusePl_SystemInit (XilSKey_EPl *InstancePtr)
	Initializes PL eFUSE with input data given. More...

u32	XilSKey_EfusePl_Program (XilSKey_EPl *InstancePtr)
	Programs PL eFUSE with input data given through InstancePtr. More...

u32	XilSKey_EfusePl_ReadStatus (XilSKey_EPl InstancePtr, u32 StatusBits)
	Reads the PL efuse status bits and gets all secure and control bits. More...

u32	XilSKey_EfusePl_ReadKey (XilSKey_EPl *InstancePtr)
	Reads the PL efuse keys and stores them in the corresponding arrays in instance structure. More...

API declarations

Variables
u32	ErrorCode
	Global variable which holds the error key. More...

XSKEfusePl_Fpga	PlFpgaFlag
	For Storing Fpga series. More...

XilSKey_JtagSlr	XilSKeyJtag
	JTAG Tap Instance. More...

Macro Definition Documentation

#define XSK_EFUSEPL_AES_ROW_END_ULTRA (27)

AES key end row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_AES_ROW_END_ULTRA_PLUS (20)

AES key end row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_AES_ROW_START_ULTRA (20)

AES key start row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_AES_ROW_START_ULTRA_PLUS (5)

AES key start row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_ARRAY_AES_DATA_BITS_IN_30th_ROW (16)

AES Data bits count in 30th Row.

#define XSK_EFUSEPL_ARRAY_AES_DATA_ROW_END (30)

AES Data End Row.

#define XSK_EFUSEPL_ARRAY_AES_DATA_ROW_START (20)

AES Data Start Row.

#define XSK_EFUSEPL_ARRAY_ECC_END_BIT_IN_A_ROW (29)

ECC End Bit position in a Row.

#define XSK_EFUSEPL_ARRAY_ECC_START_BIT_IN_A_ROW (24)

ECC Start Bit position in a Row.

#define XSK_EFUSEPL_ARRAY_FUSE_128BIT_USER_SIZE (128)

128 bit User key size

#define XSK_EFUSEPL_ARRAY_FUSE_AES_KEY_SIZE (256)

AES Key size.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_END_BIT (10)

Fuse Control Start bit.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_MAX_BITS (11)

Fuse Control max bits.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_END_BIT (24)

Redundant bit End Index.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_INDEX (14)

Redundant bit Index.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_REDUNDENT_START_BIT (14)

Redundant bit start Index.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_ROW (0)

Fuse Ctrl Row.

#define XSK_EFUSEPL_ARRAY_FUSE_CNTRL_START_BIT (0)

Fuse Control Start bit.

#define XSK_EFUSEPL_ARRAY_FUSE_USER_KEY_SIZE (32)

32 bit User key size

#define XSK_EFUSEPL_ARRAY_MAX_COL (32)

PLeFUSE Max Columns.

#define XSK_EFUSEPL_ARRAY_MAX_COL_ULTRA_PLUS (16)

Ultrascale plus max bits in a row.

#define XSK_EFUSEPL_ARRAY_MAX_ECC_BITS_IN_A_ROW (6)

Max ECC bits in a Row.

#define XSK_EFUSEPL_ARRAY_MAX_PAYLAOD_BITS_IN_A_ROW (24)

Max Pay load in Row.

#define XSK_EFUSEPL_ARRAY_MAX_ROW (32)

PLeFUSE Max Rows.

#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_BIT6 (6)

Unsupported bit.

#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_BIT7 (7)

Unsupporte bit.

#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT6 (20)

Unsupported bit.

#define XSK_EFUSEPL_ARRAY_UNSUPPORTED_RED_FOR_BIT7 (21)

Unsupported bit.

#define XSK_EFUSEPL_ARRAY_USER_DATA_BITS_IN_30th_ROW (8)

User Data bits count in 30th Row.

#define XSK_EFUSEPL_ARRAY_USER_DATA_START_ROW (31)

User Data Start Row.

#define XSK_EFUSEPL_CNTRL_MAX_BITS_ULTRA (17)

Fuse Control max bits of Ultrascale series.

#define XSK_EFUSEPL_CNTRL_ROW_END_ULTRA_PLUS (3)

Control row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_CNTRL_ROW_START_ULTRA_PLUS (2)

Control row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_CNTRL_ROW_ULTRA (1)

Control row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_CTRL_ROW_END_BIT_ULTRA (16)

Control row end bit of Ultrascale series.

#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT3_ULTRA (3)

Unsupported bits of Control register.

#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT4_ULTRA (4)

< Unsupported bit in ctrl register

#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_END_ULTRA (14)

< Unsupported bit in ctrl register

#define XSK_EFUSEPL_CTRL_ROW_UNSUPPORT_BIT_RANGE_START_ULTRA (10)

< Unsupported bit in ctrl register

#define XSK_EFUSEPL_DNA_KEY_SIZE_ULTRA (96)

DNA key size of Ultrascale series.

#define XSK_EFUSEPL_DNA_ROW_END_ULTRA_PLUS (5)

DNA row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_DNA_ROW_START_ULTRA_PLUS (0)

DNA row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_DNA_ROW_ULTRA (7)

DNA row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_END_BIT_IN_A_ROW_ULTRA (31)

FUSE end bit in a row of Ultrascale series.

#define XSK_EFUSEPL_MAX_BITS_IN_A_ROW_ULTRA (32)

Max Pay load in Row.

#define XSK_EFUSEPL_MAX_REF_CLK_FREQ 60000000

Max Ref Clk Frequency.

< Unsupported bit in ctrl register

Max Ref Clk Frequency

#define XSK_EFUSEPL_MAX_REF_CLK_FREQ 60000000

Max Ref Clk Frequency.

< Unsupported bit in ctrl register

Max Ref Clk Frequency

#define XSK_EFUSEPL_MIN_REF_CLK_FREQ 20000000

Min Ref Clk Frequency.

#define XSK_EFUSEPL_MIN_REF_CLK_FREQ 20000000

Min Ref Clk Frequency.

#define XSK_EFUSEPL_NORMAL_ULTRA (0)

Normal read selection for Ultrascale series.

#define XSK_EFUSEPL_PAGE_0_ULTRA (0)

Page 0 for Ultrascale series.

#define XSK_EFUSEPL_PAGE_1_ULTRA (1)

Page 1 for Ultrascale series.

#define XSK_EFUSEPL_REDUNDANT_ULTRA (1)

Redundant read selection for Ultrascale series.

#define XSK_EFUSEPL_RSA_HASH_SIZE_ULTRA (384)

RSA hash size of Ultrascale series.

#define XSK_EFUSEPL_RSA_ROW_END_ULTRA (23)

RSA end row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_RSA_ROW_END_ULTRA_PLUS (29)

RSA end row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_RSA_ROW_START_ULTRA (12)

RSA start row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_RSA_ROW_START_ULTRA_PLUS (6)

RSA start row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_SEC_MAX_BITS_ULTRA (7)

Secure row max bits of Ultrascale series.

#define XSK_EFUSEPL_SEC_ROW_END_BIT_ULTRA (6)

Secure row end bit of Ultrascale series.

#define XSK_EFUSEPL_SEC_ROW_ULTRA (10)

Secure row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_SEC_ROW_ULTRA_PLUS (4)

Secure row of FUSE for Ultrascale series.

#define XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA (3)

128 bit USER key end row of FUSE for Ultrascale series

#define XSK_EFUSEPL_USER_128BIT_ROW_END_ULTRA_PLUS (28)

128 bit USER key end row of FUSE for Ultrascale plus series

#define XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA (0)

128 bit USER key start row of FUSE for Ultrascale series

#define XSK_EFUSEPL_USER_128BIT_ROW_START_ULTRA_PLUS (21)

128 bit USER key start row of FUSE for Ultrascale plus series

#define XSK_EFUSEPL_USER_ROW_END_ULTRA_PLUS (31)

USER key start row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_USER_ROW_START_ULTRA_PLUS (30)

USER key start row of FUSE for Ultrascale plus series.

#define XSK_EFUSEPL_USER_ROW_ULTRA (28)

USER key start row of FUSE for Ultrascale series.

Enumeration Type Documentation

enum XSK_EfusePl_MarginOption

Read or Write eFUSE Margin Options.

Enumerator
XSK_EFUSEPL_READ_NORMAL	Margin 1.
XSK_EFUSEPL_READ_MARGIN_1	Margin 2.
XSK_EFUSEPL_READ_MARGIN_2	Margin 4.
XSK_EFUSEPL_READ_MARGIN_MAX	Max Margin 7.

enum XSKEfusePl_FuseCntrlBits

Fuse Control Row Bit Indices.

Enumerator
XSK_EFUSEPL_CNTRL_FORCE_PCYCLE_RECONFIG	Bit1 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_DISABLE_KEY_WRITE	Bit2 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_DISABLE_AES_KEY_READ	Bit3 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_READ	Bit4 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_DISABLE_FUSE_CNTRL_WRITE	Bit5 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_FORCE_USE_AES_ONLY	Bit8 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_JTAG_CHAIN_DISABLE	Bit9 of Fuse Ctrl Row.
XSK_EFUSEPL_CNTRL_BBRAM_KEY_DISABLE	Bit10 of Fuse Ctrl Row.

enum XSKEfusePl_FuseCntrlBits_Ultra

Fuse Control Row Bit Indices of Ultrascale series.

Enumerator
XSK_EFUSEPL_CNTRL_DISABLE_KEY_RD_ULTRA	Bit 0 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_RD_ULTRA	Bit 1 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_SEC_RD_ULTRA	Bit 2 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_CNTRL_WR_ULTRA	Bit 5 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_RD_ULTRA	Bit 6 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_KEY_WR_ULTRA	Bit 7 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_USER_KEY_WR_ULTRA	Bit 8 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_SEC_WR_ULTRA	Bit 8 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_RSA_KEY_WR_ULTRA	Bit 15 of Fuse Ctrl row of Ultrascale.
XSK_EFUSEPL_CNTRL_DISABLE_128BIT_USR_KEY_WR_ULTRA	Bit 16 of Fuse Ctrl row of Ultrascale.

enum XSKEfusePl_FuseSecureBits_Ultra

Fuse Secure Row Bit Indices of Ultrascale series.

Enumerator
XSK_EFUSEPL_SEC_ALLOW_ENCRYPT_ONLY	Bit 0 of Fuse Secure row of Ultrascale.
XSK_EFUSEPL_SEC_FORCE_AES_ONLY_ULTRA	Bit 1 of Fuse Secure row of Ultrascale.
XSK_EFUSEPL_SEC_RSA_AUTH_EN_ULTRA	Bit 2 of Fuse Secure row of Ultrascale.
XSK_EFUSEPL_SEC_JTAG_CHAIN_DISABLE_ULTRA	Bit 3 of Fuse Secure row of Ultrascale.
XSK_EFUSEPL_SEC_DISABLE_INTRNL_TEST_ACCESS_ULTRA	Bit 4 of Fuse Secure row of Ultrascale.
XSK_EFUSEPL_SEC_DISABLE_DECRPTR_ULTRA	Bit 5 of Fuse Secure row of Ultrascale.
XSK_EFUSEPL_SEC_ENABLE_OBFUSCATION_ULTRA	Bit 6 of fuse secure row row of Ultrascale.

Function Documentation

u32 JtagAES_Check_Ultrascale	(	u32 *	Crc,
		u8	MarginOption
	)

This function verifies the AES key of Ultrascale's EFUSE with provided CRC value.

Parameters

Crc	is a pointer to a 32 bit variable which holds the expected AES key's CRC.
MarginOption	is a variable which tells the margin option in which read operation to be performed.

Returns

Returns XST_FAILURE/XST_SUCCESS

XST_SUCCESS - If CRC is correct
XST_FAILURE - If CRC is wrong

Note: To verify AES key with provided CRC 256 bits need to be written with all ZEROS and last 32 bits with CRC. And then CTS word should be framed and read 9 rows. The keys are stored in 8 rows (20 to 27) but in UltraScale the device will read all 1s. On the 9th read (row 28), the CRC computation takes place. An extra read after the 9th read is required to read the computed CRC out (can use last row addr of 28 or row 0). The FPGA internally compares the computed CRC with the expected CRC loaded through the FUSE_KEY operation. If they match, then the expected CRC is read. If not, the FPGA will return all 1s.

void JtagRead	(	unsigned char	row,
		unsigned int *	row_data,
		unsigned char	marginOption
	)

JTAG Server Read routine.

void JtagRead_Status_Ultrascale ( u32 * Rowdata )

This function reads the status row of Ultrascale's EFUSE and updates the pointer.

Parameters

Rowdata is a pointer to a 32 bit variable which stores the status register value read from EFUSE status register.

Returns: None.

Note: Method to read FUSE register in Direct Macro Access way. For reading the status values we need send the bitstream in shift DR state. Shift in MAGIC_CTS_WRITE "FEED28AC" for ultrascale Read 64 bit data in IR read state.

void JtagRead_Ultrascale	(	u8	Row,
		u32 *	RowData,
		u8	MarginOption,
		u8	Page,
		u8	Redundant
	)

This function reads entire row of Ultrascale's EFUSE.

Parameters

Row	specifies the row number of EFUSE.
MarginOption	is a variable which tells the margin option in which read operation to be performed.
Page	tell the page of EFUSE in which the given row is located.
Redundant	is a flag to specify the bit to be programmed is Normal bit or Redundant bit. Redundant - XSK_EFUSEPL_REDUNDANT_ULTRA Normal - XSK_EFUSEPL_NORMAL_ULTRA This variable is not valid for Ultrascale plus as each row contains both redundant and normal bits upper 16 are redundant.

Returns: None.

Note: Method to read FUSE register in Direct Macro Access way. Go to TLR to clear FUSE_CTS Load FUSE_CTS instruction on IR Step to CDR/SDR to shift in 32-bits FUSE_CTS command word Shift in MAGIC_CTS_WRITE "FEED28AC" for ultrascale Read 64 bit data in IR read state.

int JtagServerInit ( XilSKey_EPl * PlInstancePtr )

JTAG Server Initialization routine.

void JtagWrite	(	unsigned char	row,
		unsigned char	bit
	)

JTAG Server Write routine.

int JtagWrite_Ultrascale	(	u8	Row,
		u8	Bit,
		u8	Page,
		u8	Redundant
	)

This function blows the fuse of Ultrascale with provided parameters.

Parameters

Row	specifies the row number of EFUSE to blow.
Bit	Specifies the bit location in the given row.
Page	tell the page of EFUSE in which the given row is located.
Redundant	is a flag to specify the bit to be programmed is Normal bit or Redundant bit. Redundant - XSK_EFUSEPL_REDUNDANT_ULTRA Normal - XSK_EFUSEPL_NORMAL_ULTRA

Returns: None.

Note: None.

Variable Documentation

u32 ErrorCode

Global variable which holds the error key.

XSKEfusePl_Fpga PlFpgaFlag

For Storing Fpga series.

Referenced by JtagAES_Check_Ultrascale(), JtagRead_Ultrascale(), and JtagWrite_Ultrascale().

XilSKey_JtagSlr XilSKeyJtag

JTAG Tap Instance.

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