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xilskey
Vitis Drivers API Documentation
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This file illustrates how to program ZynqMp efuse and read back the keys from efuse.
MODIFICATION HISTORY:
Ver Who Date Changes
4.0 vns 10/01/15 First release vns 10/20/15 Modified XilSKey_EfusePs_Example_ReadSecCtrlBits API while reading RSA authentication and PPK revokes bits status it may return 0 or BOTH_BITS_SET. So in place of TRUE added BOTH_BITS_SET. 6.0 vns 07/18/16 Removed JTAG user code programming and reading feature as it is not the part of the eFUSE 3.0 silicon. Modified XilSKey_ZynqMp_EfusePs_ReadUserKey function to XilSKey_ZynqMp_EfusePs_ReadUserFuse. Provided single bit programming facility for User FUSES. Modified RSA authentication bit set macro BOTH_BITS_SET to XSK_ZYNQMP_SEC_RSA_15BITS_SET and XSK_ZYNQMP_SEC_RSA_3BITS_SET, from silicon version 3.0 RSA authentication is possible only if all 15 bits of RSA authentication bits are set, for 1.0 and 2.0 versions only 2 bits are needed, for PPK0 REVOKE check added new macro XSK_ZYNQMP_SEC_PPK_INVLD_BITS_SET 6.2 vns 03/10/17 Added support for programming and reading LDP SC EN, FPD SC EN, LBIST, reading some of reserved bits, modified names of secure control bits Provided DNA read API call in example. 6.4 vns 02/19/18 Removed XilSKey_ZynqMp_EfusePs_CacheLoad() call as now library is been updated to reload cache after successful programming of the requested efuse bits. 6.7 psl 03/13/19 Added XSK_EFUSEPS_CHECK_AES_KEY_CRC, to check for AES key CRC if TRUE. psl 03/28/19 Corrected typos psl 04/10/19 Fixed IAR warnings. 6.8 psl 07/17/19 Added print to display CRC of AES key for CRC verification. 7.0 kpt 09/02/20 Added successfully ran print to the example in case of success 7.1 kpt 05/11/21 Added BareMetal support for programming PUF Fuses as general purpose fuses kpt 05/21/21 Added print before programming PPK hash into non-zero PPK efuses 7.5 ng 07/13/23 Added support for system device tree flow ng 08/31/23 removed redundant header file inclusion