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xilskey
Vitis Drivers API Documentation
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xilskey
Vitis Drivers API Documentation
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XEfusePl is the PL eFUSE driver instance. More...
Data Fields | |
| u32 | ForcePowerCycle |
| Following are the FUSE CNTRL bits[1:5, 8-10]. More... | |
| u32 | KeyWrite |
| If XTRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks valid only for zynq but in ultrascale If XTRUE will disable eFUSE write to FUSE_AESKEY block in Ultrascale. More... | |
| u32 | AESKeyRead |
| If XTRUE will disable eFUSE read to FUSE_AES block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in Zynq Pl.but in Ultrascale if XTRUE will disable eFUSE read to FUSE_KEY block and also disables eFUSE write to FUSE_KEY blocks. More... | |
| u32 | UserKeyRead |
| If XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in zynq but in ultrascale if XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_USER blocks. More... | |
| u32 | CtrlWrite |
| If XTRUE will disable eFUSE write to FUSE_CNTRL block in both Zynq and Ultrascale. More... | |
| u32 | RSARead |
| If XTRUE will disable eFuse read to FUSE_RSA block and also disables eFuse write to FUSE_RSA block in Ultrascale. More... | |
| u32 | UserKeyWrite |
| only For Ultrascale More... | |
| u32 | SecureWrite |
| only For Ultrascale More... | |
| u32 | RSAWrite |
| only For Ultrascale More... | |
| u32 | User128BitWrite |
| If TRUE will disable eFUSE write to 128BIT FUSE_USER block in Ultrascale. More... | |
| u32 | SecureRead |
| IF XTRUE will disable eFuse read to FUSE_SEC block and also disables eFuse write to FUSE_SEC block in Ultrascale. More... | |
| u32 | AESKeyExclusive |
| If XTRUE will force eFUSE key to be used if booting Secure Image In Zynq. More... | |
| u32 | JtagDisable |
| If XTRUE then permanently sets the Zynq ARM DAP controller in bypass mode in both zynq and ultrascale. More... | |
| u32 | UseAESOnly |
| If XTRUE will force to use Secure boot with eFUSE key only for both Zynq and Ultrascale. More... | |
| u32 | EncryptOnly |
| If XTRUE will only allow encrypted bitstreams only. More... | |
| u32 | IntTestAccessDisable |
| If XTRUE then sets the disable's Xilinx internal test access in Ultrascale. More... | |
| u32 | DecoderDisable |
| If XTRUE then permanently disables the decryptor in Ultrascale. More... | |
| u32 | RSAEnable |
| Enable RSA authentication in ultrascale. More... | |
| u32 | FuseObfusEn |
| Enable Obfuscated feature for decryption of eFUSE AES. More... | |
| u32 | ProgAESandUserLowKey |
| Following is the define to select if the user wants to select AES key and User Low Key for Zynq. More... | |
| u32 | ProgUserHighKey |
| Following is the define to select if the user wants to select User Low Key for Zynq. More... | |
| u32 | ProgAESKeyUltra |
| Following is the define to select if the user wants to select User key for Ultrascale. More... | |
| u32 | ProgUserKeyUltra |
| Following is the define to select if the user wants to select User key for Ultrascale. More... | |
| u32 | ProgRSAKeyUltra |
| Following is the define to select if the user wants to select RSA key for Ultrascale. More... | |
| u32 | ProgUser128BitUltra |
| Following is the define to select if the user wants to program 128 bit User key for Ultrascale. More... | |
| u32 | CheckAESKeyUltra |
| Following is the define to select if the user wants to read AES key for Ultrascale. More... | |
| u32 | ReadUserKeyUltra |
| Following is the define to select if the user wants to read User key for Ultrascale. More... | |
| u32 | ReadRSAKeyUltra |
| Following is the define to select if the user wants to read RSA key for Ultrascale. More... | |
| u32 | ReadUser128BitUltra |
| Following is the define to select if the user wants to read 128 bit User key for Ultrascale. More... | |
| u8 | AESKey [XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES] |
| This is the REF_CLK value in Hz. More... | |
| u8 | UserKey [XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES] |
| This is for the user_key value. More... | |
| u8 | RSAKeyHash [XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES] |
| This is for the rsa_key value for Ultrascale. More... | |
| u8 | User128Bit [XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES] |
| This is for the User 128 bit key value for Ultrascale. More... | |
| u32 | JtagMioTDI |
| TDI MIO Pin Number for ZYNQ. More... | |
| u32 | JtagMioTDO |
| TDO MIO Pin Number for ZYNQ. More... | |
| u32 | JtagMioTCK |
| TCK MIO Pin Number for ZYNQ. More... | |
| u32 | JtagMioTMS |
| TMS MIO Pin Number for ZYNQ. More... | |
| u32 | JtagMioMuxSel |
| MUX Selection MIO Pin Number for ZYNQ. More... | |
| u32 | JtagMuxSelLineDefVal |
| Value on the MUX Selection line for ZYNQ. More... | |
| u32 | JtagGpioID |
| GPIO device ID. More... | |
| u32 | HwmGpioStart |
| Hardware module Start signal's GPIO pin number. More... | |
| u32 | HwmGpioReady |
| Hardware module Ready signal's GPIO pin number. More... | |
| u32 | HwmGpioEnd |
| Hardware module End signal's GPIO pin number. More... | |
| u32 | JtagGpioTDI |
| TDI AXI GPIO pin number for Ultrascale. More... | |
| u32 | JtagGpioTDO |
| TDO AXI GPIO pin number for Ultrascale. More... | |
| u32 | JtagGpioTMS |
| TMS AXI GPIO pin number for Ultrascale. More... | |
| u32 | JtagGpioTCK |
| TCK AXI GPIO pin number for Ultrascale. More... | |
| u32 | GpioInputCh |
| AXI GPIO Channel number of all Inputs TDO. More... | |
| u32 | GpioOutPutCh |
| AXI GPIO Channel number for all Outputs TDI/TMS/TCK. More... | |
| u8 | AESKeyReadback [XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES] |
| AES key read only for Zynq. More... | |
| u8 | UserKeyReadback [XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES] |
| User key read in Ultrascale and Zynq. More... | |
| u32 | CrcOfAESKey |
| Expected AES key's CRC for Ultrascale here we can't read AES key directly. More... | |
| u8 | AESKeyMatched |
| Flag is True is AES's CRC is matched, otherwise False. More... | |
| u8 | RSAHashReadback [XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES] |
| RSA key read back for Ultrascale. More... | |
| u8 | User128BitReadBack [XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES] |
| User 128 bit key read back for Ultrascale. More... | |
| u32 | SystemInitDone |
| Internal variable to check if timer, XADC and JTAG are initialized. More... | |
| XSKEfusePl_Fpga | FpgaFlag |
| Stores Fpga series of Efuse. More... | |
| u32 | CrcToVerify |
| CRC of AES key to verify programmed AES key. More... | |
| u32 | NumSlr |
| Number of SLRs to iterate through. More... | |
| u32 | MasterSlr |
| Current SLR to iterate through. More... | |
| u32 | SlrConfigOrderIndex |
| Slr configuration order Index. More... | |
XEfusePl is the PL eFUSE driver instance.
Using this structure, user can define the eFUSE bits to be blown.
| u8 XilSKey_EPl::AESKey[XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES] |
This is the REF_CLK value in Hz.
< u32 RefClk; This is for the aes_key valuefor both Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::AESKeyExclusive |
If XTRUE will force eFUSE key to be used if booting Secure Image In Zynq.
Only for Zynq
Referenced by XilSKey_EfusePl_InitData().
| u8 XilSKey_EPl::AESKeyMatched |
Flag is True is AES's CRC is matched, otherwise False.
Only for Ultrascale
Referenced by XilSKey_EfusePl_ReadnCheck().
| u32 XilSKey_EPl::AESKeyRead |
If XTRUE will disable eFUSE read to FUSE_AES block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in Zynq Pl.but in Ultrascale if XTRUE will disable eFUSE read to FUSE_KEY block and also disables eFUSE write to FUSE_KEY blocks.
For Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u8 XilSKey_EPl::AESKeyReadback[XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES] |
AES key read only for Zynq.
Referenced by XilSKey_EfusePl_ReadnCheck().
| u32 XilSKey_EPl::CheckAESKeyUltra |
Following is the define to select if the user wants to read AES key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::CrcOfAESKey |
Expected AES key's CRC for Ultrascale here we can't read AES key directly.
Only for Ultrascale
Referenced by XilSKey_EfusePl_ReadnCheck().
| u32 XilSKey_EPl::CrcToVerify |
CRC of AES key to verify programmed AES key.
Only for Ultrascale
| u32 XilSKey_EPl::CtrlWrite |
If XTRUE will disable eFUSE write to FUSE_CNTRL block in both Zynq and Ultrascale.
For Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::DecoderDisable |
If XTRUE then permanently disables the decryptor in Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::EncryptOnly |
If XTRUE will only allow encrypted bitstreams only.
For Ultrascale only
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ForcePowerCycle |
Following are the FUSE CNTRL bits[1:5, 8-10].
If XTRUE then part has to be power cycled to be able to be reconfigured only for zynqOnly for ZYNQ
Referenced by XilSKey_EfusePl_InitData().
| XSKEfusePl_Fpga XilSKey_EPl::FpgaFlag |
Stores Fpga series of Efuse.
Referenced by JtagServerInit(), and XilSKey_EfusePl_ReadnCheck().
| u32 XilSKey_EPl::FuseObfusEn |
Enable Obfuscated feature for decryption of eFUSE AES.
only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::GpioInputCh |
AXI GPIO Channel number of all Inputs TDO.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::GpioOutPutCh |
AXI GPIO Channel number for all Outputs TDI/TMS/TCK.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::HwmGpioEnd |
Hardware module End signal's GPIO pin number.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::HwmGpioReady |
Hardware module Ready signal's GPIO pin number.
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::HwmGpioStart |
Hardware module Start signal's GPIO pin number.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::IntTestAccessDisable |
If XTRUE then sets the disable's Xilinx internal test access in Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagDisable |
If XTRUE then permanently sets the Zynq ARM DAP controller in bypass mode in both zynq and ultrascale.
for Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagGpioID |
| u32 XilSKey_EPl::JtagGpioTCK |
TCK AXI GPIO pin number for Ultrascale.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagGpioTDI |
TDI AXI GPIO pin number for Ultrascale.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagGpioTDO |
TDO AXI GPIO pin number for Ultrascale.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagGpioTMS |
TMS AXI GPIO pin number for Ultrascale.
Only for Ultrascale
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagMioMuxSel |
MUX Selection MIO Pin Number for ZYNQ.
Only for ZYNQ
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagMioTCK |
TCK MIO Pin Number for ZYNQ.
Only for ZYNQ
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagMioTDI |
TDI MIO Pin Number for ZYNQ.
Only for ZYNQ
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagMioTDO |
TDO MIO Pin Number for ZYNQ.
Only for ZYNQ
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagMioTMS |
TMS MIO Pin Number for ZYNQ.
Only for ZYNQ
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::JtagMuxSelLineDefVal |
Value on the MUX Selection line for ZYNQ.
Only for ZYNQ
Referenced by JtagServerInit(), and XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::KeyWrite |
If XTRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks valid only for zynq but in ultrascale If XTRUE will disable eFUSE write to FUSE_AESKEY block in Ultrascale.
For ZYNQ and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::MasterSlr |
Current SLR to iterate through.
Referenced by JtagServerInit().
| u32 XilSKey_EPl::NumSlr |
Number of SLRs to iterate through.
Referenced by JtagServerInit(), and main().
| u32 XilSKey_EPl::ProgAESandUserLowKey |
Following is the define to select if the user wants to select AES key and User Low Key for Zynq.
Only for Zynq
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ProgAESKeyUltra |
Following is the define to select if the user wants to select User key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ProgRSAKeyUltra |
Following is the define to select if the user wants to select RSA key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ProgUser128BitUltra |
Following is the define to select if the user wants to program 128 bit User key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ProgUserHighKey |
Following is the define to select if the user wants to select User Low Key for Zynq.
Only for Zynq
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ProgUserKeyUltra |
Following is the define to select if the user wants to select User key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ReadRSAKeyUltra |
Following is the define to select if the user wants to read RSA key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ReadUser128BitUltra |
Following is the define to select if the user wants to read 128 bit User key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::ReadUserKeyUltra |
Following is the define to select if the user wants to read User key for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::RSAEnable |
Enable RSA authentication in ultrascale.
only for Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u8 XilSKey_EPl::RSAHashReadback[XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES] |
| u8 XilSKey_EPl::RSAKeyHash[XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES] |
This is for the rsa_key value for Ultrascale.
Only for Ultrascale
| u32 XilSKey_EPl::RSARead |
If XTRUE will disable eFuse read to FUSE_RSA block and also disables eFuse write to FUSE_RSA block in Ultrascale.
only For Ultrascale If XTRUE will disable eFUSE write to FUSE_USER block in Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::RSAWrite |
only For Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::SecureRead |
IF XTRUE will disable eFuse read to FUSE_SEC block and also disables eFuse write to FUSE_SEC block in Ultrascale.
only For Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::SecureWrite |
only For Ultrascale
If XTRUE will disable eFUSE write to FUSE_RSA block in Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::SlrConfigOrderIndex |
Slr configuration order Index.
Referenced by main().
| u32 XilSKey_EPl::SystemInitDone |
Internal variable to check if timer, XADC and JTAG are initialized.
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::UseAESOnly |
If XTRUE will force to use Secure boot with eFUSE key only for both Zynq and Ultrascale.
For Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u8 XilSKey_EPl::User128Bit[XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES] |
This is for the User 128 bit key value for Ultrascale.
Only for Ultrascale
| u8 XilSKey_EPl::User128BitReadBack[XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES] |
User 128 bit key read back for Ultrascale.
Only for Ultrascale
Referenced by XilSKey_EfusePl_ReadnCheck().
| u32 XilSKey_EPl::User128BitWrite |
If TRUE will disable eFUSE write to 128BIT FUSE_USER block in Ultrascale.
only For Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u8 XilSKey_EPl::UserKey[XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES] |
This is for the user_key value.
for both Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u32 XilSKey_EPl::UserKeyRead |
If XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in zynq but in ultrascale if XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_USER blocks.
For Zynq and Ultrascale
Referenced by XilSKey_EfusePl_InitData().
| u8 XilSKey_EPl::UserKeyReadback[XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES] |
User key read in Ultrascale and Zynq.
for Ultrascale and Zynq
Referenced by XilSKey_EfusePl_ReadnCheck().
| u32 XilSKey_EPl::UserKeyWrite |
only For Ultrascale
If XTRUE will disable eFUSE write to FUSE_SEC block in Ultrascale
Referenced by XilSKey_EfusePl_InitData().