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xilsem
Vitis Drivers API Documentation
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xilsem
Vitis Drivers API Documentation
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This file has definitions of commonly used macros and data types needed for XilSEM client interface.
Data Structures | |
| struct | XSemIpiResp |
| XSemIpiResp - IPI Response Data structure. More... | |
| struct | XSemCfrErrInjData |
| XSemCfrErrInjData - CRAM Error Injection structure to hold the Error Injection Location details for CRAM: More... | |
| struct | XSemCfrStatus |
| XSemCfrStatus - CRAM Status structure to store the data read from PMC RAM registers This structure provides: More... | |
| struct | XSemNpiStatus |
| XSemNpiStatus - NPI Status structure to store the data read from PMC RAM registers. More... | |
| struct | XSem_DescriptorInfo |
| Structure to hold each descriptor information. More... | |
| struct | XSem_DescriptorData |
| Structure contains descriptor information used during SEM NPI scan. More... | |
| struct | XSem_Notifier |
| XSem_Notifier : This structure contains details of event notifications to be registered with the XilSEM server. More... | |
Macros | |
| #define | CMD_ACK_CFR_INIT (0x00010301U) |
| CRAM Initialization Acknowledgment ID. More... | |
| #define | CMD_ACK_CFR_START_SCAN (0x00010302U) |
| CRAM Start Scan Acknowledgment ID. More... | |
| #define | CMD_ACK_CFR_STOP_SCAN (0x00010303U) |
| CRAM Stop Scan Acknowledgment ID. More... | |
| #define | CMD_ACK_CFR_NJCT_ERR (0x00010304U) |
| CRAM Error Injection Acknowledgment ID. More... | |
| #define | CMD_ACK_SEM_READ_FRAME_ECC (0x0003030AU) |
| SEM Read Frame ECC Acknowledgment ID. More... | |
| #define | CMD_ACK_CFR_GET_GLDN_CRC (0x0001030CU) |
| SEM Read Golden CRC Acknowledgment ID. More... | |
| #define | CMD_ACK_CFR_GET_TF (0x0004030EU) |
| SEM Get Total Frames Acknowledgment ID. More... | |
| #define | CMD_ACK_NPI_STARTSCAN (0x00010305U) |
| NPI Start Scan Acknowledgment ID. More... | |
| #define | CMD_ACK_NPI_STOPSCAN (0x00010306U) |
| NPI Stop Scan Acknowledgment ID. More... | |
| #define | CMD_ACK_NPI_ERRINJECT (0x00010307U) |
| NPI Error Injection Acknowledgment ID. More... | |
| #define | CMD_ACK_NPI_GET_GLDN_SHA (0x00010310U) |
| NPI Get NPI Golden SHA Acknowledgment ID. More... | |
| #define | CMD_ACK_SEM_GET_CONFIG (0x00030309U) |
| SEM Get configuration Acknowledgment ID. More... | |
| #define | MAX_CRAMERR_REGISTER_CNT (7U) |
| Maximum CRAM error register count. More... | |
| #define | MAX_ADDRLOC (MAX_CRAMERR_REGISTER_CNT * 2U) |
| Maximum CRAM error High and Low register count. More... | |
| #define | MAX_NPI_SLV_SKIP_CNT (8U) |
| Maximum NPI slave skip count. More... | |
| #define | MAX_NPI_ERR_INFO_CNT (2U) |
| Maximum NPI Error info count. More... | |
| #define | PMC_RAM_BASEADDR (0XF2014000U) |
| PMC_RAM - Base Address. More... | |
| #define | PMC_RAM_SEM_NPI_STATUS (PMC_RAM_BASEADDR + 0x00000050U) |
| SEM NPI Status. More... | |
| #define | PMC_RAM_SEM_NPI_SLVSKIP_CNT0 (PMC_RAM_BASEADDR + 0x00000054U) |
| SEM NPI Slave Skip Count. More... | |
| #define | PMC_RAM_SEM_NPI_SCAN_CNT (PMC_RAM_BASEADDR + 0x00000074U) |
| SEM NPI Scan Count. More... | |
| #define | PMC_RAM_SEM_NPI_HEARTBEAT_CNT (PMC_RAM_BASEADDR + 0x00000078U) |
| SEM NPI Heartbeat Count. More... | |
| #define | PMC_RAM_SEM_NPIERR_INFO0 (PMC_RAM_BASEADDR + 0x0000007CU) |
| SEM NPI Error Info 0. More... | |
| #define | PMC_RAM_SEM_NPIERR_INFO1 (PMC_RAM_BASEADDR + 0x00000080U) |
| SEM NPI Error Info 1. More... | |
| #define | PMC_RAM_SEM_CRAM_STATUS (PMC_RAM_BASEADDR + 0X00000084U) |
| PMC_RAM_SEM_CRAM_STATUS. More... | |
| #define | PMC_RAM_SEM_CRAMERR_ADDRL0 (PMC_RAM_BASEADDR + 0X00000088U) |
| PMC_RAM_SEM_CRAMERR_ADDRL0. More... | |
| #define | PMC_RAM_SEM_CRAMERR_ADDRH0 (PMC_RAM_BASEADDR + 0X0000008CU) |
| PMC_RAM_SEM_CRAMERR_ADDRH0. More... | |
| #define | PMC_RAM_SEM_CRAM_COR_BITCNT (PMC_RAM_BASEADDR + 0X000000C0U) |
| PMC_RAM_SEM_CRAM_COR_BITCNT. More... | |
| #define | CMD_ID_CFR_INIT (0x01U) |
| Command ID for CRAM initialization. More... | |
| #define | CMD_ID_CFR_START_SCAN (0x02U) |
| Command ID for CRAM Start scan. More... | |
| #define | CMD_ID_CFR_STOP_SCAN (0x03U) |
| Command ID for CRAM Stop scan. More... | |
| #define | CMD_ID_CFR_NJCT_ERR (0x04U) |
| Command ID for CRAM error injection. More... | |
| #define | CMD_ID_CFR_RDFRAME_ECC (0x0BU) |
| Command ID for CRAM Read Frame ECC. More... | |
| #define | CMD_NPI_STARTSCAN (0x05U) |
| Command ID for NPI Start scan. More... | |
| #define | CMD_NPI_STOPSCAN (0x06U) |
| Command ID for NPI Stop scan. More... | |
| #define | CMD_NPI_ERRINJECT (0x07U) |
| Command ID for NPI error injection. More... | |
| #define | CMD_NPI_GET_GLDN_SHA (0x0AU) |
| Command ID for NPI Get Golden SHA. More... | |
| #define | CMD_EM_EVENT_REGISTER (0x08U) |
| Event Notification Register Command ID. More... | |
| #define | CMD_ID_SEM_GET_CONFIG (0x09U) |
| Command ID for SEM Get Configuration. More... | |
| #define | CMD_ID_SEM_GET_CRC (0x0CU) |
| Command ID for SEM Get Configuration for SSIT devices. More... | |
| #define | NPI_MAX_DESCRIPTORS (50U) |
| Total number of possible descriptors in NPI scan. More... | |
| #define | CFRAME_BASE_ADDRESS (0xF12D0000U) |
| Base address for CFRAME Registers. More... | |
| #define | CFRAME_ROW_OFFSET (0x2000U) |
| Offset address to select CFRAME Row instance. More... | |
| #define | CFRAME_SEU_CRC_ADDR (0x1F0U) |
| Offset address for Golden CRC. More... | |
| #define | CFRAME_LAST_BOT_ADDR (0x220U) |
| Offset address for reading Total frames in type 0, 1, 2, 3. More... | |
| #define | CFRAME_MAX_TYPE (0x07U) |
| Maximum number of frame types. More... | |
| #define | CFRAME_BIT_0_19_MASK (0x000FFFFFU) |
| MASK for 0 to 19 bits for getting Type_0, Type_4 frames. More... | |
| #define | CFRAME_BIT_20_39_MASK_LOW (0xFFF00000U) |
| MASK for 20 to 31 bits for getting Type_1, Type_5 frames. More... | |
| #define | CFRAME_BIT_20_39_MASK_HIGH (0x000000FFU) |
| MASK for 32 to 39 bits for getting Type_1, Type_5 frames. More... | |
| #define | CFRAME_BIT_20_39_SHIFT_R (20U) |
| Shift for 20 to 31 bits for getting Type_1, Type_5 frames. More... | |
| #define | CFRAME_BIT_20_39_SHIFT_L (12U) |
| Shift for 32 to 39 bits for getting Type_1, Type_5 frames. More... | |
| #define | CFRAME_BIT_40_59_MASK (0x0FFFFF00U) |
| MASK for 40 to 59 bits for getting Type_2, Type_6 frames. More... | |
| #define | CFRAME_BIT_40_59_SHIFT_R (8U) |
| Shift for 40 to 59 bits for getting Type_2, Type_6 frames. More... | |
| #define | CFRAME_BIT_60_79_MASK_LOW (0xF0000000U) |
| MASK for 60 to 63 bits for getting Type_3. More... | |
| #define | CFRAME_BIT_60_79_MASK_HIGH (0x0000FFFFU) |
| MASK for 64 to 79 bits for getting Type_3. More... | |
| #define | CFRAME_BIT_60_79_SHIFT_R (28U) |
| Shift for 60 to 63 bits for getting Type_3. More... | |
| #define | CFRAME_BIT_60_79_SHIFT_L (4U) |
| Shift for 64 to 79 bits for getting Type_3. More... | |
| #define | CMD_ID_CFR_GET_TF (0X0EU) |
| Command ID for CRAM Get Total Frames. More... | |
| #define | XSEM_NOTIFY_CRAM (0x0U) |
| SEM CRAM Module Notification ID. More... | |
| #define | XSEM_NOTIFY_NPI (0x1U) |
| SEM NPI Module Notification ID. More... | |
| #define | XSEM_EVENT_ERROR (0x1U) |
| SEM Generic Event ID. More... | |
| #define | XSEM_EVENT_CRAM_UNCOR_ECC_ERR (0x1U) |
| SEM CRAM Uncorrectable ECC Error Event. More... | |
| #define | XSEM_EVENT_CRAM_CRC_ERR (0x2U) |
| SEM CRAM Uncorrectable CRC Error Event. More... | |
| #define | XSEM_EVENT_CRAM_INT_ERR (0x3U) |
| SEM CRAM Internal or Fatal Errors. More... | |
| #define | XSEM_EVENT_CRAM_COR_ECC_ERR (0x4U) |
| SEM Correctable ECC Error Event, detected when correction is disabled. More... | |
| #define | XSEM_EVENT_NPI_CRC_ERR (0x1U) |
| SEM NPI Uncorrectable CRC Error Event. More... | |
| #define | XSEM_EVENT_NPI_DESC_FMT_ERR (0x2U) |
| NPI Unsupported Descriptor Format. More... | |
| #define | XSEM_EVENT_NPI_DESC_ABSNT_ERR (0x3U) |
| NPI Descriptors absent for Scan. More... | |
| #define | XSEM_EVENT_NPI_SHA_IND_ERR (0x4U) |
| NPI SHA Indicator mismatch error. More... | |
| #define | XSEM_EVENT_NPI_SHA_ENGINE_ERR (0x5U) |
| NPI SHA engine error. More... | |
| #define | XSEM_EVENT_NPI_PSCAN_MISSED_ERR (0x6U) |
| NPI Periodic Scan Missed Error. More... | |
| #define | XSEM_EVENT_NPI_CRYPTO_EXPORT_SET_ERR (0x7U) |
| NPI Cryptographic Accelerator Disabled error. More... | |
| #define | XSEM_EVENT_NPI_SFTY_WR_ERR (0x8U) |
| NPI Safety Write Failure. More... | |
| #define | XSEM_EVENT_NPI_GPIO_ERR (0x9U) |
| NPI GPIO Error event. More... | |
| #define | XSEM_EVENT_NPI_SELF_DIAG_FAIL (0xAU) |
| NPI Self Diagnostic event. More... | |
| #define | XSEM_EVENT_NPI_GT_ARB_FAIL (0xBU) |
| NPI GT arbitration failure event. More... | |
| #define | XSEM_EVENT_ENABLE (0x1U) |
| SEM Event Flags. More... | |
| #define | XSEM_EVENT_DISABLE (0x0U) |
| SEM Event Notification Disable. More... | |
| #define | XSEM_SSIT_MASTER_SLR_MASK (0x1U) |
| The below definitions are used for decoding response from PLM during particular SLR failure. More... | |
| #define | XSEM_SSIT_SLAVE_SLR0_MASK (0x2U) |
| SSIT slave SLR0 mask. More... | |
| #define | XSEM_SSIT_SLAVE_SLR1_MASK (0x4U) |
| SSIT slave SLR1 mask. More... | |
| #define | XSEM_SSIT_SLAVE_SLR2_MASK (0x8U) |
| SSIT slave SLR2 mask. More... | |
| #define | XSEM_SSIT_ALL_SLAVE_SLRS_MASK (0xEU) |
| SSIT all slave SLR mask. More... | |
| #define | XSEM_SSIT_ALL_SLRS_MASK (0xFU) |
| SSIT all SLR mask. More... | |
| #define | XSEM_SSIT_SLR_CHECK_MASK (0x00000001U) |
| SSIT Check SLR mask. More... | |
| #define | XSEM_SSIT_MASTER_SLR_ID (0x0U) |
| The below definitions are used for targeting SLRs while sending commands. More... | |
| #define | XSEM_SSIT_SLAVE0_SLR_ID (0x1U) |
| SSIT slave SLR0 index. More... | |
| #define | XSEM_SSIT_SLAVE1_SLR_ID (0x2U) |
| SSIT slave SLR1 index. More... | |
| #define | XSEM_SSIT_SLAVE2_SLR_ID (0x3U) |
| SSIT slave SLR2 index. More... | |
| #define | XSEM_SSIT_INVALID_SLR_ID (0x4U) |
| SSIT invalid SLR index. More... | |
| #define | XSEM_SSIT_ALL_SLRS_ID (0xFU) |
| SSIT all SLRs index. More... | |
Functions | |
| XStatus | XSem_CmdCfrInit (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to initialize CRAM scan from user application. More... | |
| XStatus | XSem_CmdCfrStartScan (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to start CRAM scan from user application. More... | |
| XStatus | XSem_CmdCfrStopScan (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to stop CRAM scan from user application. More... | |
| XStatus | XSem_CmdCfrNjctErr (XIpiPsu *IpiInst, XSemCfrErrInjData *ErrDetail, XSemIpiResp *Resp) |
| This function is used to inject an error at a valid location in CRAM from user application. More... | |
| XStatus | XSem_CmdCfrGetStatus (XSemCfrStatus *CfrStatusInfo) |
| This function is used to read all CRAM Status registers from PMC RAM and send to user application. More... | |
| XStatus | XSem_CmdCfrReadFrameEcc (XIpiPsu *IpiInst, u32 CframeAddr, u32 RowLoc, XSemIpiResp *Resp) |
| This function is used to Read frame ECC of a particular Frame. More... | |
| u32 | XSem_CmdCfrGetCrc (u32 RowIndex) |
| This function is used to read CFRAME golden CRC for a row. More... | |
| void | XSem_CmdCfrGetTotalFrames (u32 RowIndex, u32 *FrameCntPtr) |
| This function is used to read total frames in a row. More... | |
| XStatus | XSem_CmdNpiStartScan (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to start NPI scan from user application. More... | |
| XStatus | XSem_CmdNpiStopScan (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to stop NPI scan from user application. More... | |
| XStatus | XSem_CmdNpiInjectError (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to inject SHA error in NPI descriptor list (in the first NPI descriptor) from user application. More... | |
| XStatus | XSem_CmdNpiGetGldnSha (XIpiPsu *IpiInst, XSemIpiResp *Resp, XSem_DescriptorData *DescData) |
| This function is used to get golden SHA. More... | |
| XStatus | XSem_CmdNpiGetStatus (XSemNpiStatus *NpiStatusInfo) |
| This function is used to read all NPI Status registers from PMC RAM and send to user application. More... | |
| XStatus | XSem_CmdGetConfig (XIpiPsu *IpiInst, XSemIpiResp *Resp) |
| This function is used to read CRAM & NPI configuration. More... | |
| XStatus | XSem_RegisterEvent (XIpiPsu *IpiInst, XSem_Notifier *Notifier) |
| This function is used to register/un-register event notification with XilSEM Server. More... | |
| #define CFRAME_BASE_ADDRESS (0xF12D0000U) |
Base address for CFRAME Registers.
Referenced by XSem_CmdCfrGetCrc(), and XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_0_19_MASK (0x000FFFFFU) |
MASK for 0 to 19 bits for getting Type_0, Type_4 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_20_39_MASK_HIGH (0x000000FFU) |
MASK for 32 to 39 bits for getting Type_1, Type_5 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_20_39_MASK_LOW (0xFFF00000U) |
MASK for 20 to 31 bits for getting Type_1, Type_5 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_20_39_SHIFT_L (12U) |
Shift for 32 to 39 bits for getting Type_1, Type_5 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_20_39_SHIFT_R (20U) |
Shift for 20 to 31 bits for getting Type_1, Type_5 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_40_59_MASK (0x0FFFFF00U) |
MASK for 40 to 59 bits for getting Type_2, Type_6 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_40_59_SHIFT_R (8U) |
Shift for 40 to 59 bits for getting Type_2, Type_6 frames.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_60_79_MASK_HIGH (0x0000FFFFU) |
MASK for 64 to 79 bits for getting Type_3.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_60_79_MASK_LOW (0xF0000000U) |
MASK for 60 to 63 bits for getting Type_3.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_60_79_SHIFT_L (4U) |
Shift for 64 to 79 bits for getting Type_3.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_BIT_60_79_SHIFT_R (28U) |
Shift for 60 to 63 bits for getting Type_3.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_LAST_BOT_ADDR (0x220U) |
Offset address for reading Total frames in type 0, 1, 2, 3.
Referenced by XSem_CmdCfrGetTotalFrames().
| #define CFRAME_MAX_TYPE (0x07U) |
Maximum number of frame types.
Referenced by main().
| #define CFRAME_ROW_OFFSET (0x2000U) |
Offset address to select CFRAME Row instance.
Referenced by XSem_CmdCfrGetCrc(), and XSem_CmdCfrGetTotalFrames().
| #define CFRAME_SEU_CRC_ADDR (0x1F0U) |
Offset address for Golden CRC.
Referenced by XSem_CmdCfrGetCrc().
| #define CMD_ACK_CFR_GET_GLDN_CRC (0x0001030CU) |
SEM Read Golden CRC Acknowledgment ID.
| #define CMD_ACK_CFR_GET_TF (0x0004030EU) |
SEM Get Total Frames Acknowledgment ID.
| #define CMD_ACK_CFR_INIT (0x00010301U) |
CRAM Initialization Acknowledgment ID.
| #define CMD_ACK_CFR_NJCT_ERR (0x00010304U) |
CRAM Error Injection Acknowledgment ID.
| #define CMD_ACK_CFR_START_SCAN (0x00010302U) |
CRAM Start Scan Acknowledgment ID.
| #define CMD_ACK_CFR_STOP_SCAN (0x00010303U) |
CRAM Stop Scan Acknowledgment ID.
| #define CMD_ACK_NPI_ERRINJECT (0x00010307U) |
NPI Error Injection Acknowledgment ID.
Referenced by main().
| #define CMD_ACK_NPI_GET_GLDN_SHA (0x00010310U) |
NPI Get NPI Golden SHA Acknowledgment ID.
Referenced by main().
| #define CMD_ACK_NPI_STARTSCAN (0x00010305U) |
NPI Start Scan Acknowledgment ID.
Referenced by main().
| #define CMD_ACK_NPI_STOPSCAN (0x00010306U) |
NPI Stop Scan Acknowledgment ID.
Referenced by main().
| #define CMD_ACK_SEM_GET_CONFIG (0x00030309U) |
SEM Get configuration Acknowledgment ID.
Referenced by main().
| #define CMD_ACK_SEM_READ_FRAME_ECC (0x0003030AU) |
SEM Read Frame ECC Acknowledgment ID.
Referenced by main().
| #define CMD_EM_EVENT_REGISTER (0x08U) |
Event Notification Register Command ID.
Referenced by XSem_RegisterEvent().
| #define CMD_ID_CFR_GET_TF (0X0EU) |
Command ID for CRAM Get Total Frames.
| #define CMD_ID_CFR_INIT (0x01U) |
Command ID for CRAM initialization.
Referenced by XSem_CmdCfrInit().
| #define CMD_ID_CFR_NJCT_ERR (0x04U) |
Command ID for CRAM error injection.
Referenced by XSem_CmdCfrNjctErr().
| #define CMD_ID_CFR_RDFRAME_ECC (0x0BU) |
Command ID for CRAM Read Frame ECC.
Referenced by XSem_CmdCfrReadFrameEcc().
| #define CMD_ID_CFR_START_SCAN (0x02U) |
Command ID for CRAM Start scan.
Referenced by XSem_CmdCfrStartScan().
| #define CMD_ID_CFR_STOP_SCAN (0x03U) |
Command ID for CRAM Stop scan.
Referenced by XSem_CmdCfrStopScan().
| #define CMD_ID_SEM_GET_CONFIG (0x09U) |
Command ID for SEM Get Configuration.
Referenced by XSem_CmdGetConfig().
| #define CMD_ID_SEM_GET_CRC (0x0CU) |
Command ID for SEM Get Configuration for SSIT devices.
| #define CMD_NPI_ERRINJECT (0x07U) |
Command ID for NPI error injection.
Referenced by XSem_CmdNpiInjectError().
| #define CMD_NPI_GET_GLDN_SHA (0x0AU) |
Command ID for NPI Get Golden SHA.
Referenced by XSem_CmdNpiGetGldnSha().
| #define CMD_NPI_STARTSCAN (0x05U) |
Command ID for NPI Start scan.
Referenced by XSem_CmdNpiStartScan().
| #define CMD_NPI_STOPSCAN (0x06U) |
Command ID for NPI Stop scan.
Referenced by XSem_CmdNpiStopScan().
| #define MAX_ADDRLOC (MAX_CRAMERR_REGISTER_CNT * 2U) |
Maximum CRAM error High and Low register count.
| #define MAX_CRAMERR_REGISTER_CNT (7U) |
Maximum CRAM error register count.
Referenced by main(), and XSem_CmdCfrGetStatus().
| #define MAX_NPI_ERR_INFO_CNT (2U) |
Maximum NPI Error info count.
Referenced by main(), and XSem_CmdNpiGetStatus().
| #define MAX_NPI_SLV_SKIP_CNT (8U) |
Maximum NPI slave skip count.
Referenced by main(), and XSem_CmdNpiGetStatus().
| #define NPI_MAX_DESCRIPTORS (50U) |
Total number of possible descriptors in NPI scan.
| #define PMC_RAM_BASEADDR (0XF2014000U) |
PMC_RAM - Base Address.
| #define PMC_RAM_SEM_CRAM_COR_BITCNT (PMC_RAM_BASEADDR + 0X000000C0U) |
PMC_RAM_SEM_CRAM_COR_BITCNT.
Referenced by XSem_CmdCfrGetStatus().
| #define PMC_RAM_SEM_CRAM_STATUS (PMC_RAM_BASEADDR + 0X00000084U) |
PMC_RAM_SEM_CRAM_STATUS.
Referenced by XSem_CmdCfrGetStatus().
| #define PMC_RAM_SEM_CRAMERR_ADDRH0 (PMC_RAM_BASEADDR + 0X0000008CU) |
PMC_RAM_SEM_CRAMERR_ADDRH0.
Referenced by XSem_CmdCfrGetStatus().
| #define PMC_RAM_SEM_CRAMERR_ADDRL0 (PMC_RAM_BASEADDR + 0X00000088U) |
PMC_RAM_SEM_CRAMERR_ADDRL0.
Referenced by XSem_CmdCfrGetStatus().
| #define PMC_RAM_SEM_NPI_HEARTBEAT_CNT (PMC_RAM_BASEADDR + 0x00000078U) |
SEM NPI Heartbeat Count.
Referenced by XSem_CmdNpiGetStatus().
| #define PMC_RAM_SEM_NPI_SCAN_CNT (PMC_RAM_BASEADDR + 0x00000074U) |
SEM NPI Scan Count.
Referenced by XSem_CmdNpiGetStatus().
| #define PMC_RAM_SEM_NPI_SLVSKIP_CNT0 (PMC_RAM_BASEADDR + 0x00000054U) |
SEM NPI Slave Skip Count.
Referenced by XSem_CmdNpiGetStatus().
| #define PMC_RAM_SEM_NPI_STATUS (PMC_RAM_BASEADDR + 0x00000050U) |
SEM NPI Status.
Referenced by XSem_CmdNpiGetStatus().
| #define PMC_RAM_SEM_NPIERR_INFO0 (PMC_RAM_BASEADDR + 0x0000007CU) |
SEM NPI Error Info 0.
Referenced by XSem_CmdNpiGetStatus().
| #define PMC_RAM_SEM_NPIERR_INFO1 (PMC_RAM_BASEADDR + 0x00000080U) |
SEM NPI Error Info 1.
| #define XSEM_EVENT_CRAM_COR_ECC_ERR (0x4U) |
SEM Correctable ECC Error Event, detected when correction is disabled.
| #define XSEM_EVENT_CRAM_CRC_ERR (0x2U) |
SEM CRAM Uncorrectable CRC Error Event.
| #define XSEM_EVENT_CRAM_INT_ERR (0x3U) |
SEM CRAM Internal or Fatal Errors.
| #define XSEM_EVENT_CRAM_UNCOR_ECC_ERR (0x1U) |
SEM CRAM Uncorrectable ECC Error Event.
| #define XSEM_EVENT_DISABLE (0x0U) |
SEM Event Notification Disable.
| #define XSEM_EVENT_ENABLE (0x1U) |
SEM Event Flags.
SEM Event Notification Enable
| #define XSEM_EVENT_ERROR (0x1U) |
SEM Generic Event ID.
| #define XSEM_EVENT_NPI_CRC_ERR (0x1U) |
SEM NPI Uncorrectable CRC Error Event.
| #define XSEM_EVENT_NPI_CRYPTO_EXPORT_SET_ERR (0x7U) |
NPI Cryptographic Accelerator Disabled error.
| #define XSEM_EVENT_NPI_DESC_ABSNT_ERR (0x3U) |
NPI Descriptors absent for Scan.
| #define XSEM_EVENT_NPI_DESC_FMT_ERR (0x2U) |
NPI Unsupported Descriptor Format.
| #define XSEM_EVENT_NPI_GPIO_ERR (0x9U) |
NPI GPIO Error event.
| #define XSEM_EVENT_NPI_GT_ARB_FAIL (0xBU) |
NPI GT arbitration failure event.
GT arbitration failure is notified for every 5 times GT arbitration failure is encountered in NPI scanSEM Event_NPI GT Arbitration Fail
| #define XSEM_EVENT_NPI_PSCAN_MISSED_ERR (0x6U) |
NPI Periodic Scan Missed Error.
| #define XSEM_EVENT_NPI_SELF_DIAG_FAIL (0xAU) |
NPI Self Diagnostic event.
| #define XSEM_EVENT_NPI_SFTY_WR_ERR (0x8U) |
NPI Safety Write Failure.
| #define XSEM_EVENT_NPI_SHA_ENGINE_ERR (0x5U) |
NPI SHA engine error.
| #define XSEM_EVENT_NPI_SHA_IND_ERR (0x4U) |
NPI SHA Indicator mismatch error.
| #define XSEM_NOTIFY_CRAM (0x0U) |
SEM CRAM Module Notification ID.
| #define XSEM_NOTIFY_NPI (0x1U) |
SEM NPI Module Notification ID.
| #define XSEM_SSIT_ALL_SLAVE_SLRS_MASK (0xEU) |
SSIT all slave SLR mask.
| #define XSEM_SSIT_ALL_SLRS_ID (0xFU) |
SSIT all SLRs index.
| #define XSEM_SSIT_ALL_SLRS_MASK (0xFU) |
SSIT all SLR mask.
| #define XSEM_SSIT_INVALID_SLR_ID (0x4U) |
SSIT invalid SLR index.
| #define XSEM_SSIT_MASTER_SLR_ID (0x0U) |
The below definitions are used for targeting SLRs while sending commands.
SSIT master SLR index
| #define XSEM_SSIT_MASTER_SLR_MASK (0x1U) |
The below definitions are used for decoding response from PLM during particular SLR failure.
SSIT master SLR mask
| #define XSEM_SSIT_SLAVE0_SLR_ID (0x1U) |
SSIT slave SLR0 index.
| #define XSEM_SSIT_SLAVE1_SLR_ID (0x2U) |
SSIT slave SLR1 index.
| #define XSEM_SSIT_SLAVE2_SLR_ID (0x3U) |
SSIT slave SLR2 index.
| #define XSEM_SSIT_SLAVE_SLR0_MASK (0x2U) |
SSIT slave SLR0 mask.
| #define XSEM_SSIT_SLAVE_SLR1_MASK (0x4U) |
SSIT slave SLR1 mask.
| #define XSEM_SSIT_SLAVE_SLR2_MASK (0x8U) |
SSIT slave SLR2 mask.
| #define XSEM_SSIT_SLR_CHECK_MASK (0x00000001U) |
SSIT Check SLR mask.