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xilsecure
Vitis Drivers API Documentation
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xilsecure
Vitis Drivers API Documentation
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This is the header file which contains ZynqMP AES core hardware definitions.
MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ------------------------------------------------------- 4.0 vns 03/11/19 Initial release 4.6 am 09/17/21 Resolved compiler warnings 4.7 am 11/26/21 Resolved doxygen warning
Macros | |
| #define | XSECURE_CSU_AES_BASE (0xFFCA1000U) |
| CSU AES base address. More... | |
| #define | XSECURE_CSU_PCAP_STATUS (0xFFCA3010U) |
| CSU PCAP Status reg. More... | |
| #define | XSECURE_CSU_PCAP_STATUS_PCAP_WR_IDLE_MASK (0X00000001U) |
| PCAP Write Idle. More... | |
Register Map | |
Register offsets for the AES module. | |
| #define | XSECURE_CSU_AES_STS_OFFSET (0x00U) |
| AES Status. More... | |
| #define | XSECURE_CSU_AES_KEY_SRC_OFFSET (0x04U) |
| AES Key Source. More... | |
| #define | XSECURE_CSU_AES_KEY_LOAD_OFFSET (0x08U) |
| AES Key Load Reg. More... | |
| #define | XSECURE_CSU_AES_START_MSG_OFFSET (0x0CU) |
| AES Start Message. More... | |
| #define | XSECURE_CSU_AES_RESET_OFFSET (0x10U) |
| AES Reset Register. More... | |
| #define | XSECURE_CSU_AES_KEY_CLR_OFFSET (0x14U) |
| AES Key Clear. More... | |
| #define | XSECURE_CSU_AES_CFG_OFFSET (0x18U) |
| AES Operational Mode. More... | |
| #define | XSECURE_CSU_AES_KUP_WR_OFFSET (0x1CU) |
| AES KUP Write Control. More... | |
| #define | XSECURE_CSU_AES_KUP_0_OFFSET (0x20U) |
| AES Key Update 0. More... | |
| #define | XSECURE_CSU_AES_KUP_1_OFFSET (0x24U) |
| AES Key Update 1. More... | |
| #define | XSECURE_CSU_AES_KUP_2_OFFSET (0x28U) |
| AES Key Update 2. More... | |
| #define | XSECURE_CSU_AES_KUP_3_OFFSET (0x2CU) |
| AES Key Update 3. More... | |
| #define | XSECURE_CSU_AES_KUP_4_OFFSET (0x30U) |
| AES Key Update 4. More... | |
| #define | XSECURE_CSU_AES_KUP_5_OFFSET (0x34U) |
| AES Key Update 5. More... | |
| #define | XSECURE_CSU_AES_KUP_6_OFFSET (0x38U) |
| AES Key Update 6. More... | |
| #define | XSECURE_CSU_AES_KUP_7_OFFSET (0x3CU) |
| AES Key Update 7. More... | |
| #define | XSECURE_CSU_AES_IV_0_OFFSET (0x40U) |
| AES IV 0. More... | |
| #define | XSECURE_CSU_AES_IV_1_OFFSET (0x44U) |
| AES IV 1. More... | |
| #define | XSECURE_CSU_AES_IV_2_OFFSET (0x48U) |
| AES IV 2. More... | |
| #define | XSECURE_CSU_AES_IV_3_OFFSET (0x4CU) |
| AES IV 3. More... | |
| #define XSECURE_CSU_AES_BASE (0xFFCA1000U) |
CSU AES base address.
Referenced by XSecure_AesInitialize().
| #define XSECURE_CSU_AES_CFG_OFFSET (0x18U) |
AES Operational Mode.
Referenced by XSecure_AesDecrypt(), XSecure_AesDecryptInit(), and XSecure_AesEncryptInit().
| #define XSECURE_CSU_AES_IV_0_OFFSET (0x40U) |
AES IV 0.
Referenced by XSecure_AesDecrypt().
| #define XSECURE_CSU_AES_IV_1_OFFSET (0x44U) |
AES IV 1.
| #define XSECURE_CSU_AES_IV_2_OFFSET (0x48U) |
AES IV 2.
| #define XSECURE_CSU_AES_IV_3_OFFSET (0x4CU) |
AES IV 3.
Referenced by XSecure_AesDecrypt(), and XSecure_AesDecryptUpdate().
| #define XSECURE_CSU_AES_KEY_CLR_OFFSET (0x14U) |
AES Key Clear.
Referenced by XSecure_AesDecrypt(), XSecure_AesDecryptInit(), and XSecure_AesEncryptInit().
| #define XSECURE_CSU_AES_KEY_LOAD_OFFSET (0x08U) |
AES Key Load Reg.
| #define XSECURE_CSU_AES_KEY_SRC_OFFSET (0x04U) |
AES Key Source.
| #define XSECURE_CSU_AES_KUP_0_OFFSET (0x20U) |
AES Key Update 0.
Referenced by XSecure_AesDecrypt(), XSecure_AesDecryptInit(), and XSecure_AesEncryptInit().
| #define XSECURE_CSU_AES_KUP_1_OFFSET (0x24U) |
AES Key Update 1.
| #define XSECURE_CSU_AES_KUP_2_OFFSET (0x28U) |
AES Key Update 2.
| #define XSECURE_CSU_AES_KUP_3_OFFSET (0x2CU) |
AES Key Update 3.
| #define XSECURE_CSU_AES_KUP_4_OFFSET (0x30U) |
AES Key Update 4.
| #define XSECURE_CSU_AES_KUP_5_OFFSET (0x34U) |
AES Key Update 5.
| #define XSECURE_CSU_AES_KUP_6_OFFSET (0x38U) |
AES Key Update 6.
| #define XSECURE_CSU_AES_KUP_7_OFFSET (0x3CU) |
AES Key Update 7.
| #define XSECURE_CSU_AES_KUP_WR_OFFSET (0x1CU) |
AES KUP Write Control.
| #define XSECURE_CSU_AES_RESET_OFFSET (0x10U) |
AES Reset Register.
Referenced by XSecure_AesDecrypt(), XSecure_AesDecryptInit(), XSecure_AesDecryptUpdate(), XSecure_AesEncryptInit(), XSecure_AesEncryptUpdate(), and XSecure_AesReset().
| #define XSECURE_CSU_AES_START_MSG_OFFSET (0x0CU) |
AES Start Message.
Referenced by XSecure_AesDecryptInit(), and XSecure_AesEncryptInit().
| #define XSECURE_CSU_AES_STS_OFFSET (0x00U) |
AES Status.
Referenced by XSecure_AesDecryptUpdate().
| #define XSECURE_CSU_PCAP_STATUS (0xFFCA3010U) |
CSU PCAP Status reg.
| #define XSECURE_CSU_PCAP_STATUS_PCAP_WR_IDLE_MASK (0X00000001U) |
PCAP Write Idle.