Overview

This example demonstrates generation of shared secret using Elliptic Curve Diffie–Hellman Key Exchange (ECDH).

To build this application, xilmailbox library must be included in BSP and xilsecure must be in client mode This example is supported for Versal Net devices.

Note: Procedure to link and compile the example for the default ddr less designs

The default linker settings places a software stack, heap and data in DDR memory. For this example to work, any data shared between client running on A72/R5/PL and server running on PMC, should be placed in area which is acccessible to both client and server.

Following is the procedure to compile the example on OCM or any memory region which can be accessed by server

    1. Open example linker script(lscript.ld) in Vitis project and section to memory mapping should
            be updated to point all the required sections to shared memory(OCM or TCM)
            using a memory region drop down selection

                                    OR

    1. In linker script(lscript.ld) user can add new memory section in source tab as shown below
            .sharedmemory : {
                    . = ALIGN(4);
                    __sharedmemory_start = .;
                    *(.sharedmemory)
                    *(.sharedmemory.*)
                    *(.gnu.linkonce.d.*)
                    __sharedmemory_end = .;
                    } > versal_cips_0_pspmc_0_psv_ocm_ram_0_psv_ocm_ram_0

            2. In this example ".data" section elements that are passed by reference to the server-side should
               be stored in the above shared memory section. To make it happen in below example,
       replace ".data" in attribute section with ".sharedmemory". For example,
               static const u8 Hash_P384[] __attribute__ ((section (".data.Hash_P384")))
                                    should be changed to
               static const u8 Hash_P384[] __attribute__ ((section (".sharedmemory.Hash_P384")))

To keep things simple, by default the cache is disabled for this example

The endianness selected in the example should be in sync with the endianness selected for Xilsecure server which is part of PLM.

MODIFICATION HISTORY:

Ver   Who  Date        Changes
----- ---- ---------- -------------------------------------------------------
1.0   har  06/20/2023 Initial release

Note

Overview

Procedure to link and compile the example for the default ddr less designs