This is the header file which contains definitions for the versal_net hardware registers.

MODIFICATION HISTORY:

Ver   Who  Date        Changes
----- ---- -------- -------------------------------------------------------
1.00  bm   07/06/2022 Initial release
      ma   07/08/2022 Add support for storing procs to PMC RAM based on ID
      ma   07/08/2022 Added support for secure lockdown
      ma   07/13/2022 Added RTC_CONTROL_SLVERR_EN_MASK macro
      ma   07/20/2022 Move PMC_PSM_ERR_REG_OFFSET to xplmi_error_common.h
      kpt  07/21/2022 Added DME FIPS cache register
      bm   07/22/2022 Update EAM logic for In-Place PLM Update
      bm   07/22/2022 Added compatibility check for In-Place PLM Update
      ma   07/25/2022 Enhancements to secure lockdown code
1.01  bm   11/07/2022 Clear SSS Cfg Error in SSSCfgSbiDma for Versal Net
      ng   11/11/2022 Fixed doxygen file name error
      sk   01/13/2023 Added Register/Mask defines for PMX LPD FPD CPM domain
1.02  bm   04/28/2023 Added IRO_SWAP and sysmon related macros
      bm   05/22/2023 Update current CDO command offset in GSW Error Status
      bm   07/06/2023 Refactored Proc logic to more generic logic
      kpt  07/10/2023 Added macros related to DDRMC status check
      am   07/11/2023 Reduced the trace event buffer length to accommodate
                      IHT OP data store address
      ng   07/13/2023 Added support for system device-tree flow
      ro   08/03/2023 Updated XPAR_XIICPS_0_BASEADDR macro
1.03  ma   10/10/2023 Enable Slave Error for PSM_GLOBAL
      mss  10/31/2023 Added PMC_GLOBAL_PMC_FW_ERR_CR_FLAG_MASK macro
      pre  14/12/2023 Fixed compilation warnings
      mss  01/09/2024 Added XPLMI_TOTAL_CHUNK_SIZE macro for Validating address
      pre  01/22/2024 Updated XPlmi_SetPmcIroFreq to support both ES1 and
                      production samples
      bm   03/02/2024 Make SD drive number logic order independent
      sk   05/07/2024 Added defines for WDT and IPI registers
1.04  sk   08/26/2024 Updated EAM support for Versal 2VE and 2VM Devices
      yog  09/09/2024 Updated ASU memory region addresses
      ma   09/20/2024 Added PMC_TAP_VERSION_COSIM mask for COSIM platform
                      Also, corrected XPLMI_PLATFORM_MASK value
      yog  09/30/2024 Corrected ASU RAM high address
          nb   10/07/2024 Add PMC IOMODULE interrupt for power interrupts
      pre  12/09/2024 Added METAHEADER_INSTANCE_ADDRESS and RTCA_LEN_IN_BYTES macros
      pre  01/02/2025 Increased metaheader space from 4k to 8k with start address as 0xF2012000U
      ma   01/07/2025 Added ASU specific register defines
      pre  01/09/2024 Added addresses needed for PCIE error handling
      sk   02/20/2025 Added register address for LPD,OCM,FPD regions
      sk   03/12/2025 Added define for UFS config
      sk   03/17/2025 Added TCM address range defines for all RPU clusters
      pre  04/07/2025 Hash verification skip for non-secure boot in export control enabled devices

Note