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xilpdi
Vitis Drivers API Documentation
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xilpdi
Vitis Drivers API Documentation
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This is the header file which contains versal specific definitions for the PDI.
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -------------------------------------------------------
1.00 bm 07/06/2022 Initial release
bm 09/13/2022 Reduce maximum number of partitions and images
1.01 har 11/17/2022 Added macros for bh_auth attribute in Bootheader
ng 11/23/2022 Fixed doxygen file name error
sk 01/11/2023 Added macro for Image Store as SBD
1.02 kpt 12/04/2023 Added XilPdi_BootHdr
2.01 mb 08/10/2024 Added macro for JTAG as SBD.Data Structures | |
| struct | XilPdi_BootHdrFwRsvd |
| Structure to store the Boot Header PMC FW fields. More... | |
| struct | XilPdi_BootHdr |
| Structure to store the boot header table details. More... | |
| struct | XilPdi_ImgHdrTbl |
| Structure to store the image header table details. More... | |
| struct | XilPdi_PrtnHdr |
| Structure to store the partition header details. More... | |
XilPdi Definitions | |
| #define | XIH_BH_IMG_ATTRB_BH_AUTH_MASK (0xC000U) |
| Boot header Attr fields. More... | |
| #define | XIH_BH_IMG_ATTRB_BH_AUTH_SHIFT (14U) |
| #define | XIH_BH_IMG_ATTRB_BH_AUTH_VALUE (0x3U) |
| #define | XIH_MAX_PRTNS (20U) |
| #define | XIH_MAX_IMGS (10U) |
| #define | XIH_IHT_ATTR_SBD_MASK (0xFC0U) |
| Secondary Boot Device (SBD) in IHT Attributes. More... | |
| #define | XIH_IHT_ATTR_SBD_SHIFT (0x6U) |
| #define | XIH_IHT_ATTR_SBD_SAME (0x0U) |
| #define | XIH_IHT_ATTR_SBD_QSPI32 (0x1U) |
| #define | XIH_IHT_ATTR_SBD_QSPI24 (0x2U) |
| #define | XIH_IHT_ATTR_SBD_SD_0 (0x4U) |
| #define | XIH_IHT_ATTR_SBD_SD_1 (0x5U) |
| #define | XIH_IHT_ATTR_SBD_SD_LS (0x6U) |
| #define | XIH_IHT_ATTR_SBD_EMMC (0x7U) |
| #define | XIH_IHT_ATTR_SBD_USB (0x8U) |
| #define | XIH_IHT_ATTR_SBD_PCIE (0xAU) |
| #define | XIH_IHT_ATTR_SBD_OSPI (0xCU) |
| #define | XIH_IHT_ATTR_SBD_SMAP (0xDU) |
| #define | XIH_IHT_ATTR_SBD_JTAG (0xEU) |
| #define | XIH_IHT_ATTR_SBD_SD_0_RAW (0xFU) |
| #define | XIH_IHT_ATTR_SBD_SD_1_RAW (0x10U) |
| #define | XIH_IHT_ATTR_SBD_SD_LS_RAW (0x11U) |
| #define | XIH_IHT_ATTR_SBD_EMMC_RAW (0x12U) |
| #define | XIH_IHT_ATTR_SBD_EMMC_0 (0x13U) |
| #define | XIH_IHT_ATTR_SBD_EMMC_0_RAW (0x14U) |
| #define | XIH_IHT_ATTR_IMAGE_STORE (0x15U) |
| #define | XIH_PH_ATTRB_HIVEC_MASK (0x800000U) |
| Prtn Attribute fields. More... | |
| #define | XIH_PH_ATTRB_ENDIAN_MASK (0x40000U) |
| #define | XIH_PH_ATTRB_A72_EXEC_ST_MASK (0x0008U) |
| #define | XIH_PH_ATTRB_PRTN_TYPE_RSVD (0x0000000U) |
| Prtn Attribute Values. More... | |
| #define | XIH_PH_ATTRB_PRTN_TYPE_ELF (0x1000000U) |
| #define | XIH_PH_ATTRB_PRTN_TYPE_CDO (0x2000000U) |
| #define | XIH_PH_ATTRB_PRTN_TYPE_CFI_GSC_UNMASK (0x7000000U) |
| #define | XIH_PH_ATTRB_PRTN_OWNER_PLM (0x00000U) |
| #define | XIH_PH_ATTRB_HASH_SHA3 (0x3000U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_NONE (0x0000U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_A72_0 (0x100U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_A72_1 (0x200U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_R5_0 (0x500U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_R5_1 (0x600U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_R5_L (0x700U) |
| #define | XIH_PH_ATTRB_DSTN_CPU_PSM (0x800U) |
| #define | XIH_PH_ATTRB_A72_EXEC_ST_AA64 (0x0000U) |
| #define | XIH_ATTRB_A72_EXEC_ST_SHIFT_DIFF (3U) |
| Below is the bit mapping of fields in the ATF Handoff parameters with that of Prtn header. More... | |
| #define | XIH_ATTRB_ENDIAN_SHIFT_DIFF (17U) |
| #define | XIH_ATTRB_TR_SECURE_SHIFT_DIFF (2U) |
| #define | XIH_ATTRB_TARGET_EL_SHIFT_DIFF (2U) |
| #define | XIH_ATTRB_EL_MASK (0x18U) |
| #define | XIH_PRTN_FLAGS_EL_2 (0x10U) |
| #define | XIH_PRTN_FLAGS_EL_3 (0x18U) |
| #define | XIH_PRTN_FLAGS_DSTN_CPU_A72_0 (0x00U) |
| #define | XIH_PRTN_FLAGS_DSTN_CPU_A72_1 (0x20U) |
| #define | XIH_BH_META_HDR_OFFSET (0xC4U) |
| Offset to the metaheader offset field present in boot header. More... | |
| #define | XIH_BH_PRAM_ADDR (0xF201E000U) |
| Boot header address in PRAM copied by ROM. More... | |
| #define | XIH_BH_PUF_HD_OFFSET (0x918U) |
| Boot header PUF fields. More... | |
| #define | XIH_BH_PUF_CHASH_OFFSET (0xF18U) |
| BootHeader PUF CHASH offset. More... | |
| #define | XIH_BH_PUF_AUX_OFFSET (0xF1CU) |
| BootHeader PUF auxiliary offset. More... | |
| #define XIH_ATTRB_A72_EXEC_ST_SHIFT_DIFF (3U) |
Below is the bit mapping of fields in the ATF Handoff parameters with that of Prtn header.
The number of bits shifted is is based on the difference between these two offsets
ATFHandoffParams PrtnHdr Shift Parameter PrtnFlags PrtnAttrb difference
Exec State 0 3 3 right ENDIAN 1 18 17 right SECURE 2 0 2 left EL 3:4 1:2 2 left CPU_A72 5:6 8:10
| #define XIH_BH_IMG_ATTRB_BH_AUTH_MASK (0xC000U) |
Boot header Attr fields.
| #define XIH_BH_META_HDR_OFFSET (0xC4U) |
Offset to the metaheader offset field present in boot header.
| #define XIH_BH_PRAM_ADDR (0xF201E000U) |
Boot header address in PRAM copied by ROM.
Referenced by XilPdi_ReadBootHdr().
| #define XIH_BH_PUF_AUX_OFFSET (0xF1CU) |
BootHeader PUF auxiliary offset.
| #define XIH_BH_PUF_CHASH_OFFSET (0xF18U) |
BootHeader PUF CHASH offset.
| #define XIH_BH_PUF_HD_OFFSET (0x918U) |
Boot header PUF fields.
BootHeader PUF HD offset.
| #define XIH_IHT_ATTR_SBD_MASK (0xFC0U) |
Secondary Boot Device (SBD) in IHT Attributes.
| #define XIH_PH_ATTRB_HIVEC_MASK (0x800000U) |
Prtn Attribute fields.
| #define XIH_PH_ATTRB_PRTN_TYPE_RSVD (0x0000000U) |
Prtn Attribute Values.