xilnvm
Vitis Drivers API Documentation
xnvm_bbram_hw.h File Reference

Overview

This file contains NVM library BBRAM modules hardware register definitions. 

MODIFICATION HISTORY:
Ver   Who  Date        Changes






1.0   mmd  04/01/2019 Initial release
2.1     am   08/19/2020 Resolved MISRA C violations.
2.4   kal  07/13/2021 Fixed doxygen warnings
3.1   skg  10/23/2022 Added comments for macros
3.3   ng   11/22/2023 Fixed doxygen grouping
3.5   har  03/13/2025 Added XNVM_BBRAM_8_MEM_REG macro definition
 



Macros


BBRAM Controller Base Address


#define XNVM_BBRAM_BASE_ADDR   (0xF11F0000U)


 BBRAM Base Address.  More...


 


BBRAM Controller Registers


#define XNVM_BBRAM_STATUS_REG   (0x00U)


 < BBRAM Control Register offsets  More...


 



#define XNVM_BBRAM_CTRL_REG   (0x04U)


 



#define XNVM_BBRAM_PGM_MODE_REG   (0x08U)


 



#define XNVM_BBRAM_AES_CRC_REG   (0x0CU)


 



#define XNVM_BBRAM_0_REG   (0x10U)


 



#define XNVM_BBRAM_8_REG   (0x30U)


 



#define XNVM_BBRAM_MSW_LOCK_REG   (0x4CU)


 


STATUS register


#define XNVM_BBRAM_STATUS_PGM_MODE_DONE   ((u32)0x01U << 0U)


 < BBRAM Status Register definition  More...


 



#define XNVM_BBRAM_STATUS_ZEROIZED   ((u32)0x01U << 4U)


 



#define XNVM_BBRAM_STATUS_AES_CRC_DONE   ((u32)0x01U << 8U)


 



#define XNVM_BBRAM_STATUS_AES_CRC_PASS   ((u32)0x01U << 9U)


 


CTRL register


#define XNVM_BBRAM_CTRL_START_ZEROIZE   ((u32)0x01U << 0U)


 < BBRAM Ctrl Start Zeroize mask  More...


 


PGM_MODE register


#define XNVM_EFUSE_PGM_MODE_PASSCODE   (0x757BDF0DU)


 < PGM_MODE Passcode  More...


 


MSW_LOCK register definition


#define XNVM_BBRAM_MSW_LOCK   ((u32)0x01U << 0U)


 < BBRAM MSW LOCK Mask  More...


 


Timeout in term of number of times status register polled


#define XNVM_BBRAM_PGM_MODE_TIMEOUT_VAL   (0x400U)


 < PGM_MODE Timeout  More...


 


#define XNVM_BBRAM_AES_CRC_DONE_TIMEOUT_VAL   (0x400U)


 ZEROIZE Timeout.  More...


 



#define XNVM_BBRAM_ZEROIZE_TIMEOUT_VAL   (0x400U)


 




Macro Definition Documentation






      

        

          #define XNVM_BBRAM_AES_CRC_DONE_TIMEOUT_VAL   (0x400U)
        

      





ZEROIZE Timeout. 











      

        

          #define XNVM_BBRAM_BASE_ADDR   (0xF11F0000U)
        

      





BBRAM Base Address. 



Referenced by XNvm_BbramZeroize().











      

        

          #define XNVM_BBRAM_CTRL_START_ZEROIZE   ((u32)0x01U << 0U)
        

      





< BBRAM Ctrl Start Zeroize mask 



Referenced by XNvm_BbramZeroize().











      

        

          #define XNVM_BBRAM_MSW_LOCK   ((u32)0x01U << 0U)
        

      





< BBRAM MSW LOCK Mask 



Referenced by XNvm_BbramLockUsrDataWrite().











      

        

          #define XNVM_BBRAM_PGM_MODE_TIMEOUT_VAL   (0x400U)
        

      





< PGM_MODE Timeout 


CRC_DONE Timeout 











      

        

          #define XNVM_BBRAM_STATUS_PGM_MODE_DONE   ((u32)0x01U << 0U)
        

      





< BBRAM Status Register definition 











      

        

          #define XNVM_BBRAM_STATUS_REG   (0x00U)
        

      





< BBRAM Control Register offsets 



Referenced by XNvm_BbramZeroize().











      

        

          #define XNVM_EFUSE_PGM_MODE_PASSCODE   (0x757BDF0DU)
        

      





< PGM_MODE Passcode