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xilnvm
Vitis Drivers API Documentation
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This file contains eFuse functions of xilnvm library and provides the access to program eFUSE.
MODIFICATION HISTORY:
Ver Who Date Changes
3.0 kal 07/12/2022 Initial release 3.1 kal 11/01/2022 Make Revocation id number 0 as valid to align with ROM behaviour skg 11/08/2022 Added In Body comments for APIs 3.2 har 02/22/2023 Added API to program ROM Rsvd eFUSEs. vss 03/14/2023 Fixed compilation warining kum 04/11/2023 Added Env monitor before efuse programming kpt 07/26/2023 Removed XNvm_EfuseReadCacheRange kpt 07/26/2023 Fix security review comments kpt 08/28/2023 Fix SW-BP-REDUNDANCY while assigning Status to CloseStatus kpt 09/05/2023 Fix SW-BP-REDUNDANCY in XNvm_EfusePrgmIv and XNvm_EfuseWriteDmeRevoke kpt 09/09/2023 Avoid returning XST_SUCCESS in case of glitch yog 09/13/2023 Used XNvm_IsDmeModeEn() API for reading DME Mode vss 12/31/2023 Added support for Program the eFuse protection bits only once kal 01/24/2024 Fixed doxygen warnings 3.3 kpt 02/01/2024 XNvm_EfuseWriteRoSwapEn only when RoSwap is non-zero vss 04/01/2024 Fixed MISRA-C 12.1 violation and EXPRESSION_WITH_MAGIC_NUMBERS coverity warning 3.4 kal 05/07/2024 Fixed issue in all DME keys programming vss 07/26/2024 Corrected offchipids to be programmed kal 11/13/2024 Corrected logic in XNvm_EfuseWriteRevocationID function obs 04/21/2025 Fixed GCC Warnings.
Macros | |
| #define | XNVM_EFUSE_ERROR_BYTE_SHIFT (8U) |
| Byte shift used in error code. More... | |
| #define | XNVM_EFUSE_ERROR_NIBBLE_SHIFT (4U) |
| Nibble shift used in error code. More... | |
| #define | XNVM_EFUSE_MAX_FIPS_VERSION (7U) |
| Max Value of FIPS version. More... | |
| #define | XNVM_EFUSE_MAX_FIPS_MODE (0xFFU) |
| Max value of FIPS mode. More... | |
| #define | XNVM_EFUSE_BITS_IN_A_BYTE (8U) |
| Number of bits in a byte. More... | |
| #define | XNVM_EFUSE_SEC_DEF_VAL_ALL_BIT_SET (0xFFFFFFFFU) |
| Secure Default Value for a register. More... | |
| #define | XNVM_EFUSE_BYTE_MASK (0xFF) |
| Mask for 8 bits. More... | |
| #define | REVERSE_POLYNOMIAL (0x82F63B78U) |
| Value used in CRC calculation to reverse a polynomial. More... | |
| #define | XNVM_EFUSE_SKIP_VERIFY (1U) |
| Skip verification of eFuses after programming. More... | |
| #define | XNVM_EFUSE_PROGRAM_VERIFY (0U) |
| Verify eFuses after programming. More... | |
| #define | XNVM_EFUSE_CRC_SALT (0x000000FFU) |
| CRC salt value. More... | |
| #define | XNVM_EFUSE_REVOKE_ID_127 (127U) |
| Efuse revoke ID. More... | |
| #define | XNVM_EFUSE_PUF_SEC_CTRL_INVLD_MASK 0xE0000000U |
| Mask for PUF control bits in PUF_ECC_PUF_CTRL register in EFUSE_CACHE module. More... | |
| #define | XNVM_EFUSE_PUF_CTRL_PUF_REGEN_DIS_MASK 0x80000000U |
| Mask for PUF_REGEN_DISABLE. More... | |
| #define | XNVM_EFUSE_PUF_CTRL_PUF_HD_INVLD_MASK 0x40000000U |
| Mask for PUF_HD_INVLD. More... | |
| #define | XNVM_EFUSE_PUF_CTRL_PUF_REGIS_DIS_MASK 0x20000000U |
| Mask for PUF_REGIS_DIS. More... | |
| #define | XNVM_EFUSE_DME_KEY_SIZE_IN_BYTES (48U) |
| DME key size in bytes. More... | |
| #define | XNVM_EFUSE_DME_0_USER_EFUSE_CACHE_OFFSET (0x240U) |
| DME 0 corresponding User eFuse offset. More... | |
| #define | XNVM_EFUSE_DME_1_USER_EFUSE_CACHE_OFFSET (0x270U) |
| DME 1 corresponding User eFuse offset. More... | |
| #define | XNVM_EFUSE_DME_2_USER_EFUSE_CACHE_OFFSET (0x2A0U) |
| DME 2 corresponding User eFuse offset. More... | |
| #define | XNVM_EFUSE_DME_3_USER_EFUSE_CACHE_OFFSET (0x2D0U) |
| DME 3 corresponding User eFuse offset. More... | |
| #define | XNVM_EFUSE_PPK_HASH_UPPER_WORD_START_OFFSET (8U) |
| PPK HASH upper 128 bit hash start word offset. More... | |
| #define | XNVM_EFUSE_LAST_ROW_IN_PAGE (255U) |
| Row number of last eFuse row in page. More... | |
| #define | XNVM_EFUSE_CACHE_ANLG_TRIM_0 (0xF1250004U) |
| ANLG_TRIM_0 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ANLG_TRIM_1 (0xF1250008U) |
| ANLG_TRIM_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ANLG_TRIM_2 (0xF125000CU) |
| ANLG_TRIM_2 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_IP_DISABLE_1 (0xF125001CU) |
| IP_DISABLE_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_DNA_0 (0xF1250020U) |
| DNA_0 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_DNA_1 (0xF1250024U) |
| DNA_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_DNA_2 (0xF1250028U) |
| DNA_2 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_DNA_3 (0xF125002CU) |
| DNA_3 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_BRAM (0xF1250098U) |
| TRIM_BRAM eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_URAM (0xF125009CU) |
| TRIM_URAM eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_PMC_BISR_0 (0xF12500D8U) |
| PMC_BISR_0 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_PMC_BISR_1 (0xF12500DCU) |
| PMC_BISR_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ANLG_TRIM_5 (0xF12500E0U) |
| ANLG_TRIM_5 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ANLG_TRIM_6 (0xF12500F4U) |
| ANLG_TRIM_6 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ANLG_TRIM_7 (0xF12500F8U) |
| ANLG_TRIM_7 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ME_ID_CODE (0xF12500FCU) |
| ME_ID_CODE eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_EXPORT_DFT (0xF125018CU) |
| EXPORT_DFT eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_4 (0xF1250190U) |
| TRIM_AMS_4 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_5 (0xF1250194U) |
| TRIM_AMS_5 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_6 (0xF1250198U) |
| TRIM_AMS_6 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_7 (0xF125019CU) |
| TRIM_AMS_7 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_8 (0xF12501A0U) |
| TRIM_AMS_8 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_9 (0xF12501A4U) |
| TRIM_AMS_9 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_10 (0xF12501A8U) |
| TRIM_AMS_10 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_11 (0xF12501ACU) |
| TRIM_AMS_11 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_12 (0xF12501B0U) |
| TRIM_AMS_12 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_CFRM_VGG_0 (0xF12501B4U) |
| TRIM_CFRM_VGG_0 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_CFRM_VGG_1 (0xF12501B8U) |
| TRIM_CFRM_VGG_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_CFRM_VGG_2 (0xF12501BCU) |
| TRIM_CFRM_VGG_2 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_CRAM (0xF12501C0U) |
| TRIM_CRAM eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_NIDB_0 (0xF12501C4U) |
| NIDB_0 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_NIDB_1 (0xF12501C8U) |
| NIDB_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_NIDB_2 (0xF12501CCU) |
| NIDB_2 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_0 (0xF12501F4U) |
| TRIM_AMS_0 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_1 (0xF12501F8U) |
| TRIM_AMS_1 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_2 (0xF12501FCU) |
| TRIM_AMS_2 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_TRIM_AMS_3 (0xF1250200U) |
| TRIM_AMS_3 eFuse cache offset. More... | |
| #define | XNVM_EFUSE_CACHE_ME_ID_CODE_3_0_MASK (0x0000000FU) |
| ME_ID_CODE_3_0_MASK. More... | |
| #define | XNVM_CRC_DATA_WORD_COUNT (37U) |
| CRC DATA word count. More... | |
| #define | XNVM_CRC_DATA_BYTE_COUNT (XNVM_CRC_DATA_WORD_COUNT * XNVM_WORD_LEN) |
| CRC data byte count. More... | |
Functions | |
| int | XNvm_EfuseWriteAesKey (u32 EnvDisFlag, XNvm_AesKeyType KeyType, XNvm_AesKey *EfuseKey) |
| This function is used to take care of prerequisites to program below eFuses AES key User key 0 User key 1. More... | |
| int | XNvm_EfuseWritePpkHash (u32 EnvDisFlag, XNvm_PpkType PpkType, XNvm_PpkHash *EfuseHash) |
| This function is used to to take care of prerequisitis to program below eFuses PPK0_HASH PPK1_HASH PPK2_HASH. More... | |
| int | XNvm_EfuseWriteIv (u32 EnvDisFlag, XNvm_IvType IvType, XNvm_Iv *EfuseIv) |
| This function is used to to take care of prerequisitis to program below IV eFuses XNVM_EFUSE_ERR_WRITE_META_HEADER_IV XNVM_EFUSE_ERR_WRITE_BLK_OBFUS_IV XNVM_EFUSE_ERR_WRITE_PLM_IV XNVM_EFUSE_ERR_WRITE_DATA_PARTITION_IV. More... | |
| int | XNvm_EfuseWriteGlitchConfigBits (u32 EnvDisFlag, u32 GlitchConfig) |
| This function is used to program Glitch Configuration given by the user. More... | |
| int | XNvm_EfuseWriteDecOnly (u32 EnvDisFlag) |
| This function is used to program below DEC_ONLY fuses. More... | |
| int | XNvm_EfuseWriteRevocationID (u32 EnvDisFlag, u32 RevokeIdNum) |
| This function writes Revocation eFuses. More... | |
| int | XNvm_EfuseWriteOffChipRevokeID (u32 EnvDisFlag, u32 OffchipIdNum) |
| This function programs OffChip Revoke eFuses. More... | |
| int | XNvm_EfuseWriteMiscCtrlBits (u32 EnvDisFlag, u32 MiscCtrlBits) |
| This function programs MiscCtrl eFuses. More... | |
| int | XNvm_EfuseWriteSecCtrlBits (u32 EnvDisFlag, u32 SecCtrlBits) |
| This function programs SecCtrl eFuses. More... | |
| int | XNvm_EfuseWriteMisc1Bits (u32 EnvDisFlag, u32 Misc1Bits) |
| This function programs Misc1Ctrl eFuses. More... | |
| int | XNvm_EfuseWriteBootEnvCtrlBits (u32 EnvDisFlag, u32 BootEnvCtrlBits) |
| This function programs BootEnvCtrl eFuses. More... | |
| int | XNvm_EfuseWriteFipsInfo (u32 EnvDisFlag, u32 FipsMode, u32 FipsVersion) |
| This function is used to to take care of prerequisitis to program FIPS mode and FIPS version eFuses. More... | |
| int | XNvm_EfuseWriteUds (u32 EnvDisFlag, XNvm_Uds *EfuseUds) |
| This function programs UDS eFuses. More... | |
| int | XNvm_EfuseWriteDmeUserKey (u32 EnvDisFlag, XNvm_DmeKeyType KeyType, XNvm_DmeKey *EfuseKey) |
| This function programs DME userkey eFuses. More... | |
| int | XNvm_EfuseWriteDmeRevoke (u32 EnvDisFlag, XNvm_DmeRevoke RevokeNum) |
| This function programs DME Revoke eFuses. More... | |
| int | XNvm_EfuseWriteDisableInplacePlmUpdate (u32 EnvDisFlag) |
| This function programs PLM_UPDATE eFuse. More... | |
| int | XNvm_EfuseWriteBootModeDisable (u32 EnvDisFlag, u32 BootModeMask) |
| This function programs BootModeDisable eFuses. More... | |
| int | XNvm_EfuseWriteDmeMode (u32 EnvDisFlag, u32 DmeMode) |
| This function programs DmeMode eFuses. More... | |
| int | XNvm_EfuseWriteCrc (u32 EnvDisFlag, u32 Crc) |
| This function programs EFUSE_CRC_SALT eFuses. More... | |
| int | XNvm_EfuseWritePuf (const XNvm_EfusePufHdAddr *PufHelperData) |
| This function programs PUF ctrl and PUF helper data, Chash and Aux. More... | |
| int | XNvm_EfuseWritePufSecCtrl (u32 EnvDisFlag, u32 PufCtrlBits) |
| This function programs Puf control bits specified by user. More... | |
| int | XNvm_EfuseCacheLoadNPrgmProtectionBits (void) |
| This function reloads the cache of eFUSE so that can be directly read from cache and programs required protections eFuses. More... | |
| int | XNvm_EfuseWriteRomRsvdBits (u32 EnvDisFlag, u32 RomRsvdBits) |
| This function programs ROM Rsvd Bits eFuses. More... | |