xilnvm
Vitis Drivers API Documentation
versal_gen/versal/server/xnvm_efuse.h File Reference

Overview

This file contains function declarations of eFuse APIs.

MODIFICATION HISTORY:
Ver   Who  Date       Changes


1.0 kal 08/16/2019 Initial release 2.0 kal 02/27/2020 Added eFuse wrapper APIs to program AES keys, PPK hash, Revocation ID, SecCtrl eFuses, Puf HD and APIs to read eFuse Cache values. kal 03/03/2020 Added protection eFuse row programming. 2.1 rpo 06/06/2020 Support added to write glitch configuration data. rpo 06/08/2020 Support added to program eFuse halt boot bits to stop at ROM stage. am 08/19/2020 Resolved MISRA C violations. kal 09/03/2020 Fixed Security CoE review comments am 10/13/2020 Resolved MISRA C violations ana 10/15/2020 Updated doxygen comments. 2.3 kal 01/07/2021 Added support to SecurityMisc1, BootEnvCtrl,MiscCtrl and remaining eFuses in SecCtrl eFuse rows programming and reading kal 01/28/2021 Added new error code for glitch detection kal 02/20/2021 Added new error codes for detecting voltage and temparature out of range cases har 04/21/2021 Fixed warnings for R5 processor kpt 05/12/2021 Added sysmon instance to the function prototype of individual write API's kpt 05/20/2021 Added support for programming PUF efuses as general purpose data 2.4 kal 07/25/2021 Moved common structures between client and server to xnvm_defs.h 2.5 har 01/03/2022 Renamed NumOfPufFuses as NumOfPufFusesRows 3.0 kal 07/12/2022 Moved common code to xnvm_efuse_common.h 3.1 skg 10/25/2022 Added comments for macros skg 12/07/2022 Added Additional PPKs related enums and macros 3.2 kum 04/11/2023 Moved env common code to xnvm_efuse_common.h vss 09/19/2023 Fixed MISRA-C Rule 2.5 violation 3.3 har 12/04/2023 Added support for HWTSTBITS_DIS and PMC_SC_EN efuse bits vss 12/31/2023 Added support for Program the eFuse protection bits only once kpt 02/21/2024 Added generic handler vss 02/23/2024 Added IPI support for eFuse read and write ng 12/12/2023 Fixed doxygen grouping

 

Data Structures

struct  XNvm_EfuseUserData
 user efuses details More...
 
struct  XNvm_EfusePufHd
 Defines Puf helper data. More...
 
struct  XNvm_EfuseData
 This structure defines sub structures of Versal eFuses to be blown. More...
 

Macros

#define XNVM_PUF_FORMATTED_SYN_DATA_LEN_IN_WORDS   (127U)
 < PUF syndrome length definations for Versal eFuse More...
 
#define XNVM_PUF_ROW_UPPER_NIBBLE_MASK   (0xF0000000U)
 User efuses start, end and number of efuses definations. More...
 
#define XNVM_USER_FUSE_START_NUM   (1U)
 User eFuse start number. More...
 
#define XNVM_USER_FUSE_END_NUM   (63U)
 User eFuse end number. More...
 
#define XNVM_NUM_OF_USER_FUSES   (XNVM_USER_FUSE_END_NUM)
 Number of user eFuses. More...
 
#define XNVM_MAX_REVOKE_ID_FUSES
 Maximum eFuses in a row. More...
 
EFUSE masks
#define XNVM_EFUSE_PROTECTION_BIT_SECURITY_CONTROL_MASK
 < Protection bit masks of various eFuses More...
 
#define XNVM_EFUSE_PROTECTION_BIT_SECURITY_MISC_0_MASK
 
#define XNVM_EFUSE_PROTECTION_BIT_PPK_0_HASH_MASK
 
#define XNVM_EFUSE_PROTECTION_BIT_META_HEADER_IV_MASK
 
#define XNVM_EFUSE_BOOTENVCTRL_ANLGTRIMX_TRIMAMS_MASK   ((u32)1U << XNVM_EFUSE_ROW_37_PROT_COLUMN)
 
#define XNVM_EFUSE_PROTECTION_BIT_MISC_CTRL_MASK   ((u32)1U << XNVM_EFUSE_ROW_40_PROT_COLUMN)
 
#define XNVM_EFUSE_PROTECTION_BIT_PUF_CHASH_MASK   ((u32)1U << XNVM_EFUSE_ROW_42_PROT_COLUMN)
 
#define XNVM_EFUSE_PROTECTION_BIT_SECURITY_MISC_1_MASK   ((u32)1U << XNVM_EFUSE_ROW_58_PROT_COLUMN)
 

Enumerations

enum  XNvm_SecCtrlBitColumns {
  XNVM_EFUSE_SEC_AES_DIS = 0, XNVM_EFUSE_SEC_JTAG_ERROUT_DIS, XNVM_EFUSE_SEC_JTAG_DIS, XNVM_EFUSE_SEC_HWTSTBITS_DIS,
  XNVM_EFUSE_SEC_IP_DIS_WRLK = 5, XNVM_EFUSE_SEC_PPK0_WRLK, XNVM_EFUSE_SEC_PPK1_WRLK, XNVM_EFUSE_SEC_PPK2_WRLK,
  XNVM_EFUSE_SEC_AES_CRC_LK_BIT_0, XNVM_EFUSE_SEC_AES_CRC_LK_BIT_1, XNVM_EFUSE_SEC_AES_WRLK, XNVM_EFUSE_SEC_USER_KEY0_CRC_LK,
  XNVM_EFUSE_SEC_USER_KEY0_WRLK, XNVM_EFUSE_SEC_USER_KEY1_CRC_LK, XNVM_EFUSE_SEC_USER_KEY1_WRLK, XNVM_EFUSE_SEC_PUF_SYN_LK,
  XNVM_EFUSE_SEC_PUF_TEST2_DIS, XNVM_EFUSE_SEC_PUF_DIS, XNVM_EFUSE_SEC_SECDBG_DIS_BIT_0, XNVM_EFUSE_SEC_SECDBG_DIS_BIT_1,
  XNVM_EFUSE_SEC_SECLOCKDBG_DIS_BIT_0, XNVM_EFUSE_SEC_SECLOCKDBG_DIS_BIT_1, XNVM_EFUSE_SEC_PMC_SC_EN_BIT_0, XNVM_EFUSE_SEC_PMC_SC_EN_BIT_1,
  XNVM_EFUSE_SEC_PMC_SC_EN_BIT_2, XNVM_EFUSE_SEC_SVD_WRLK, XNVM_EFUSE_SEC_DNA_WRLK, XNVM_EFUSE_SEC_BOOTENV_WRLK,
  XNVM_EFUSE_SEC_CACHE_WRLK, XNVM_EFUSE_SEC_REG_INIT_DIS_BIT_0, XNVM_EFUSE_SEC_REG_INIT_DIS_BIT_1
}
 eFuse control bits More...
 
enum  XNvm_MiscCtrlBitColumns {
  XNVM_EFUSE_MISC_PPK0_INVALID_BIT_0 = 2, XNVM_EFUSE_MISC_PPK0_INVALID_BIT_1, XNVM_EFUSE_MISC_PPK1_INVALID_BIT_0, XNVM_EFUSE_MISC_PPK1_INVALID_BIT_1,
  XNVM_EFUSE_MISC_PPK2_INVALID_BIT_0, XNVM_EFUSE_MISC_PPK2_INVALID_BIT_1, XNVM_EFUSE_MISC_SAFETY_MISSION_EN, XNVM_EFUSE_MISC_PPK3_INVALID_BIT_0 = 9,
  XNVM_EFUSE_MISC_PPK3_INVALID_BIT_1, XNVM_EFUSE_MISC_PPK4_INVALID_BIT_0, XNVM_EFUSE_MISC_PPK4_INVALID_BIT_1, XNVM_EFUSE_MISC_LBIST_EN = 14,
  XNVM_EFUSE_MISC_CRYPTO_KAT_EN, XNVM_EFUSE_MISC_ADD_PPK_EN_BIT_0 = 16, XNVM_EFUSE_MISC_ADD_PPK_EN_BIT_1, XNVM_EFUSE_MISC_HALT_BOOT_ENV_BIT_0 = 19,
  XNVM_EFUSE_MISC_HALT_BOOT_ENV_BIT_1, XNVM_EFUSE_MISC_HALT_BOOT_ERROR_BIT_0, XNVM_EFUSE_MISC_HALT_BOOT_ERROR_BIT_1, XNVM_EFUSE_MISC_GD_ROM_MONITOR_EN = 29,
  XNVm_EFUSE_MISC_GD_HALT_BOOT_EN_BIT_0, XNVm_EFUSE_MISC_GD_HALT_BOOT_EN_BIT_1
}
 

Functions

int XNvm_EfuseWrite (const XNvm_EfuseData *WriteNvm)
 This function is used as a wrapper to program below eFuses AES key User key 0 User key 1 PPK0/PPK1/PPK2/PPK3/PPK4 hash IVs Revocation Ids User Fuses Secure and Control bits. More...
 
int XNvm_EfuseWriteIVs (XNvm_EfuseIvs *EfuseIv, XSysMonPsv *SysMonInstPtr)
 This function programs the eFUSEs with the IV. More...
 
int XNvm_EfuseRevokePpk (XNvm_PpkType PpkRevoke, XSysMonPsv *SysMonInstPtr)
 This function revokes the Ppk. More...
 
int XNvm_EfuseWriteRevocationId (u32 RevokeId, XSysMonPsv *SysMonInstPtr)
 This function writes Revocation eFuses. More...
 
int XNvm_EfuseWriteUserFuses (XNvm_EfuseUserData *WriteUserFuses, XSysMonPsv *SysMonInstPtr)
 This function Programs User eFuses. More...
 
int XNvm_EfuseReadIv (XNvm_Iv *EfuseIv, XNvm_IvType IvType)
 This function is used to read IV eFUSE bits from cache. More...
 
int XNvm_EfuseReadRevocationId (u32 *RevokeFusePtr, XNvm_RevocationId RevokeFuseNum)
 This function reads the Revocation Fuse from eFUSE cache. More...
 
int XNvm_EfuseReadUserFuses (const XNvm_EfuseUserData *UserFusesData)
 This function reads User eFuses from Cache. More...
 
int XNvm_EfuseReadMiscCtrlBits (XNvm_EfuseMiscCtrlBits *MiscCtrlBits)
 This function is used to read the miscellaneous eFUSE control bits from cache. More...
 
int XNvm_EfuseReadSecCtrlBits (XNvm_EfuseSecCtrlBits *SecCtrlBits)
 This function reads secure control bits and CRC_EN register bits from eFUSE cache. More...
 
int XNvm_EfuseReadPpkHash (XNvm_PpkHash *EfusePpk, XNvm_PpkType PpkType)
 This function reads the Ppk Hash from eFUSE cache. More...
 
int XNvm_EfuseReadDecOnly (u32 *DecOnly)
 This function reads DEC only fuses from eFUSE cache. More...
 
int XNvm_EfuseReadDna (XNvm_Dna *EfuseDna)
 This function is used to read Dna eFUSE bits from cache. More...
 
int XNvm_EfuseReadCacheRange (u32 StartRow, u8 RowCount, u32 *RowData)
 This function reads 32-bit rows from eFUSE cache. More...
 
int XNvm_EfuseWritePuf (const XNvm_EfusePufHd *PufHelperData)
 This function programs the eFUSEs with the PUF helper data. More...
 
int XNvm_EfuseReadPuf (XNvm_EfusePufHd *PufHelperData)
 This function reads the PUF helper data from eFUSE cache. More...
 
int XNvm_EfuseReadPufSecCtrlBits (XNvm_EfusePufSecCtrlBits *PufSecCtrlBits)
 This function is used to read the Puf eFUSE secure control bits from cache. More...
 
int XNvm_EfuseReadSecMisc1Bits (XNvm_EfuseSecMisc1Bits *SecMisc1Bits)
 This function is used to read the security miscellaneous1 bits from cache. More...
 
int XNvm_EfuseReadBootEnvCtrlBits (XNvm_EfuseBootEnvCtrlBits *BootEnvCtrlBits)
 This function reads the Boot Environmental Control bits from cache. More...
 
int XNvm_EfuseReadOffchipRevokeId (u32 *OffchipIdPtr, XNvm_OffchipId OffchipIdNum)
 This function reads the Offchip revoke eFuse value from eFUSE cache. More...
 

Macro Definition Documentation

#define XNVM_EFUSE_PROTECTION_BIT_SECURITY_CONTROL_MASK
Value:
((u32)1U << XNVM_EFUSE_ROW_43_0_PROT_COLUMN) | \
#define XNVM_EFUSE_ROW_43_1_PROT_COLUMN
&lt; EFUSE column numbers
Definition: versal_gen/versal/server/xnvm_efuse_hw.h:99

< Protection bit masks of various eFuses

#define XNVM_MAX_REVOKE_ID_FUSES
Value:
(XNVM_NUM_OF_REVOKE_ID_FUSES \
* XNVM_EFUSE_MAX_BITS_IN_ROW)

Maximum eFuses in a row.

Referenced by XNvm_EfuseWriteOffChipRevokeID(), XNvm_EfuseWriteRevocationID(), and XNvm_EfuseWriteRevocationId().

#define XNVM_NUM_OF_USER_FUSES   (XNVM_USER_FUSE_END_NUM)

Number of user eFuses.

Referenced by XNvm_EfuseReadUserFuses().

#define XNVM_PUF_FORMATTED_SYN_DATA_LEN_IN_WORDS   (127U)

< PUF syndrome length definations for Versal eFuse

Referenced by XNvm_EfuseReadPuf().

#define XNVM_PUF_ROW_UPPER_NIBBLE_MASK   (0xF0000000U)

User efuses start, end and number of efuses definations.

#define XNVM_USER_FUSE_END_NUM   (63U)

User eFuse end number.

Referenced by XNvm_EfuseReadUserFuses().

#define XNVM_USER_FUSE_START_NUM   (1U)

User eFuse start number.

Referenced by XNvm_EfuseReadUserFuses().

Enumeration Type Documentation

Enumerator
XNVM_EFUSE_MISC_PPK0_INVALID_BIT_0 

Ppk0 invalid bit 0.

XNVM_EFUSE_MISC_PPK0_INVALID_BIT_1 

Ppk0 invalid bit 1.

XNVM_EFUSE_MISC_PPK1_INVALID_BIT_0 

Ppk1 invalid bit 0.

XNVM_EFUSE_MISC_PPK1_INVALID_BIT_1 

Ppk1 invalid bit 1.

XNVM_EFUSE_MISC_PPK2_INVALID_BIT_0 

Ppk2 invalid bit 0.

XNVM_EFUSE_MISC_PPK2_INVALID_BIT_1 

Ppk2 invalid bit 1.

XNVM_EFUSE_MISC_SAFETY_MISSION_EN 

Safety mission enable.

XNVM_EFUSE_MISC_PPK3_INVALID_BIT_0 

Ppk3 invalid bit 0.

XNVM_EFUSE_MISC_PPK3_INVALID_BIT_1 

Ppk3 invalid bit 1.

XNVM_EFUSE_MISC_PPK4_INVALID_BIT_0 

Ppk4 invalid bit 0.

XNVM_EFUSE_MISC_PPK4_INVALID_BIT_1 

Ppk4 invalid bit 1.

XNVM_EFUSE_MISC_LBIST_EN 

Lbist enable.

XNVM_EFUSE_MISC_CRYPTO_KAT_EN 

Crypto kat enable.

XNVM_EFUSE_MISC_ADD_PPK_EN_BIT_0 

Additional PPK enable bit 0.

XNVM_EFUSE_MISC_ADD_PPK_EN_BIT_1 

Additional PPK enable bit 1.

XNVM_EFUSE_MISC_HALT_BOOT_ENV_BIT_0 

Halt boot env bit 0.

XNVM_EFUSE_MISC_HALT_BOOT_ENV_BIT_1 

Halt boot env bit 1.

XNVM_EFUSE_MISC_HALT_BOOT_ERROR_BIT_0 

Halt boot error bit 0.

XNVM_EFUSE_MISC_HALT_BOOT_ERROR_BIT_1 

Halt boot error bit 1.

XNVM_EFUSE_MISC_GD_ROM_MONITOR_EN 

Rom monitor enable.

XNVm_EFUSE_MISC_GD_HALT_BOOT_EN_BIT_0 

Halt boot enable bit 0.

XNVm_EFUSE_MISC_GD_HALT_BOOT_EN_BIT_1 

Halt boot enable bit 1.

eFuse control bits

< This structer defines Security control bits

Enumerator
XNVM_EFUSE_SEC_AES_DIS 

Aes disable.

XNVM_EFUSE_SEC_JTAG_ERROUT_DIS 

Jtag error out disable.

XNVM_EFUSE_SEC_JTAG_DIS 

Jtag disable.

XNVM_EFUSE_SEC_HWTSTBITS_DIS 

Hardware testbit mode disable.

XNVM_EFUSE_SEC_IP_DIS_WRLK 

IP disable.

XNVM_EFUSE_SEC_PPK0_WRLK 

PPK0_WRLK.

XNVM_EFUSE_SEC_PPK1_WRLK 

PPK1_WRLK.

XNVM_EFUSE_SEC_PPK2_WRLK 

PPK2_WRLK.

XNVM_EFUSE_SEC_AES_CRC_LK_BIT_0 

Aes crc lock bit 0.

XNVM_EFUSE_SEC_AES_CRC_LK_BIT_1 

Aes crc lock bit 1.

XNVM_EFUSE_SEC_AES_WRLK 

Aes boot key write lock.

XNVM_EFUSE_SEC_USER_KEY0_CRC_LK 

User key0 crc lock.

XNVM_EFUSE_SEC_USER_KEY0_WRLK 

User key0 write lock.

XNVM_EFUSE_SEC_USER_KEY1_CRC_LK 

User key1 crc lock.

XNVM_EFUSE_SEC_USER_KEY1_WRLK 

User key1 write lock.

XNVM_EFUSE_SEC_PUF_SYN_LK 

Puf syndrome lock.

XNVM_EFUSE_SEC_PUF_TEST2_DIS 

Puf test2 disable.

XNVM_EFUSE_SEC_PUF_DIS 

Puf disable.

XNVM_EFUSE_SEC_SECDBG_DIS_BIT_0 

Secure debug disable bit 0.

XNVM_EFUSE_SEC_SECDBG_DIS_BIT_1 

Secure debug disable bit 1.

XNVM_EFUSE_SEC_SECLOCKDBG_DIS_BIT_0 

Secure lock debug disable bit 0.

XNVM_EFUSE_SEC_SECLOCKDBG_DIS_BIT_1 

Secure lock debug disable bit 1.

XNVM_EFUSE_SEC_PMC_SC_EN_BIT_0 

PMC_SC Enable bit 0.

XNVM_EFUSE_SEC_PMC_SC_EN_BIT_1 

PMC_SC Enable bit 1.

XNVM_EFUSE_SEC_PMC_SC_EN_BIT_2 

PMC_SC Enable bit 2.

XNVM_EFUSE_SEC_SVD_WRLK 

SVD write lock.

XNVM_EFUSE_SEC_DNA_WRLK 

DNA write lock.

XNVM_EFUSE_SEC_BOOTENV_WRLK 

Boot env write lock.

XNVM_EFUSE_SEC_CACHE_WRLK 

Cache write lock.

XNVM_EFUSE_SEC_REG_INIT_DIS_BIT_0 

Reg init disable bit 0.

XNVM_EFUSE_SEC_REG_INIT_DIS_BIT_1 

Reg init disable bit 1.