Partial reconfiguration(PR) is the ability for a portion of an FPGA to be reprogrammed while the remainder of the system stays unchanged.

Dynamic PR allows device reconfiguration during runtime while rest of the Device is still functioning.

This file contains the example using xilfpga library to transfer the user provided Partial Reconfiguration Bitstream into ZynqMP PL region. Before loading this example please make sure static Bitstream associated with the PR design has been loaded into the PL.

MODIFICATION HISTORY:

Ver   Who     Date     Changes



4.2   adk     08/03/18  Initial Release.
4.2      adk     08/23/18  Added bitstream size define.
5.0   Nava       02/06/19  Updated the example to sync with 5.0 version API's
5.2   Nava    02/14/20  Removed unwanted header file inclusion.
5.2   Nava    02/27/20  Added support for Versal Platform.
5.3   Nava    06/16/20  Modified the date format from dd/mm to mm/dd.
6.0   Nava    12/14/20  In XFpga_PL_BitStream_Load() API the argument
                        AddrPtr_Size is being used for multiple purposes.
                        Use of the same variable for multiple purposes can
                        make it more difficult for a person to read (or)
                        understand the code and also it leads to a safety
                        violation. fixes this  issue by adding a separate
                        function arguments to read KeyAddr and
                        Size(Bitstream size).
6.1   Nava    09/13/21  Fixed compilation warning.