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xilasu
Vitis Drivers API Documentation
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xilasu
Vitis Drivers API Documentation
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This header file defines the structures that are used for shared memory communication between the client and the server.
The structures include definitions for message formats, shared memory control blocks, and any other relevant data structures needed for inter-process communication
MODIFICATION HISTORY:
Ver Who Date Changes
1.0 vns 06/04/24 Initial release ma 07/08/24 Add task based approach at queue level ma 07/23/24 Update XASU_RESPONSE_STATUS_INDEX with 0 1.1 ma 12/12/24 Updated command states ma 02/19/25 Updated handling of same priority queue requests in round robin scheduling ma 02/26/25 Corrected XASU_CHANNEL_RESERVED_MEM define value
Data Structures | |
| struct | XAsu_ReqBuf |
| This structure is the request buffer. More... | |
| struct | XAsu_RespBuf |
| This structure is the response buffer. More... | |
| struct | XAsu_ChannelQueueBuf |
| This structure is the channel's queue buffer. More... | |
| struct | XAsu_ChannelQueue |
| This structure is the channel's queue which is of 8 buffers. More... | |
| struct | XAsu_ChannelMemory |
| This struture is the channel's memory. More... | |
| struct | XAsu_CommChannel |
| This structure contains information of each communication channel. More... | |
| struct | XAsu_CommChannelInfo |
| This structure contains information of all communication channels. More... | |
Macros | |
| #define | XASU_MAX_BUFFERS (8U) |
| Maximum request and response buffers. More... | |
| #define | XASU_CHANNEL_RESERVED_MEM (1188U) |
| Reserved memory in channel. More... | |
| #define | XASU_COMMAND_IS_PRESENT (0x1U) |
| Command is written by client. More... | |
| #define | XASU_COMMAND_IN_PROGRESS (0x2U) |
| Command is in progress by ASUFW. More... | |
| #define | XASU_COMMAND_WAITING_FOR_RESOURCE (0x3U) |
| Command is waiting for required resources. More... | |
| #define | XASU_COMMAND_DMA_WAIT_COMPLETE (0x4U) |
| Command DMA wait operation is complete. More... | |
| #define | XASU_COMMAND_EXECUTION_COMPLETE (0x5U) |
| Command execution is complete by ASUFW. More... | |
| #define | XASU_RESPONSE_IS_PRESENT (0x1U) |
| Response is written by ASUFW. More... | |
| #define | XASU_RESPONSE_STATUS_INDEX (0U) |
| Response status index in response buffer. More... | |
| #define | XASU_RESPONSE_BUFF_ADDR_INDEX (1U) |
| Response buffer address index in response buffer. More... | |
| #define | XASU_COMMAND_ID_MASK (0x0000003FU) |
| Mask for command ID in header. More... | |
| #define | XASU_UNIQUE_REQ_ID_MASK (0x00000FC0U) |
| Mask for command unique reqest ID. More... | |
| #define | XASU_UNIQUE_REQ_ID_SHIFT (6U) |
| Shift value for unique request ID. More... | |
| #define | XASU_UNIQUE_ID_MAX (XASU_MAX_BUFFERS << 1U) |
| Maximum unique IDs generated by ASU. More... | |
| #define | XASU_MODULE_ID_MASK (0x0003F000U) |
| Mask for module ID. More... | |
| #define | XASU_MODULE_ID_SHIFT (12U) |
| Shift value for module ID. More... | |
| #define | XASU_COMMAND_LENGTH_MASK (0x00FC0000U) |
| Mask for command length in header. More... | |
| #define | XASU_COMMAND_LENGTH_SHIFT (18U) |
| Shift for command length. More... | |
| #define | XASU_COMMAND_REQ_ARGS (22U) |
| Command arguments count. More... | |
| #define | XASU_COMMAND_RESP_ARGS (17U) |
| Response arguments count. More... | |
| #define | XASU_RTCA_BASEADDR (0xEBE40000U) |
| ASUFW run time configuration area base address. More... | |
| #define | XASU_RTCA_COMM_CHANNEL_INFO_ADDR (XASU_RTCA_BASEADDR + 0x10U) |
| Communication channel info register address. More... | |
| #define | XASU_MAX_IPI_CHANNELS (8U) |
| Maximum IPI channels supported by ASUFW. More... | |
| #define | XASU_CHANNEL_MEMORY_OFFSET (0x1000U) |
| Channel memory offset. More... | |