Overview

This file contains the software API definition of the Xilinx XDMA PCIe IP (XDma_0).

This driver provides "C" function interface to application/upper layer to access the hardware.

Features The driver provides its user with entry points

To initialize and configure itself and the hardware
To access PCIe configuration space locally

Driver Initialization & Configuration

The XDmaPcie_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:

XDmaPcie_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in xdmapcie_g.c. This is setup by the tools.
XDmaPcie_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.

Interrupt Management

The XDmaPcie driver provides interrupt management functions. It allows the caller to enable/disable each individual interrupt as well as get/clear pending interrupts. Implementation of callback handlers is left to the user.

Note

MODIFICATION HISTORY:

Ver Who Date Changes

1.0 tk 01/30/2019 First release

Data Structures
struct	XDmaPcie_Config
	This typedef contains IP hardware configuration information. More...

struct	XDmaPcie
	The XDmaPcie driver instance data. More...

struct	XDmaPcie_BarAddr
	The user is required to use this strucuture when reading or writing translation vector between local bus BARs and XDMA PCIe BARs. More...

Macros
#define	MAX_BARS 6
	No BAR allocation for Bridge. More...

#define	REQ_SIZE (MAX_BARS * sizeof(unsigned long))
	Required size for BAR Alignment. More...

#define	XDMAPCIE_VSEC1 0x00
	First VSEC Register. More...

#define	XDMAPCIE_VSEC2 0x01
	Second VSEC Register. More...

#define	XDmaPcie_IsLinkUp(InstancePtr)
	Check whether link is up or not. More...

#define	XDmaPcie_IsEcamBusy(InstancePtr)
	Check whether ECAM is busy or not. More...

Functions
XDmaPcie_Config *	XDmaPcie_LookupConfig (u16 DeviceId)
	Lookup the device configuration based on the unique device ID. More...

int	XDmaPcie_CfgInitialize (XDmaPcie InstancePtr, XDmaPcie_Config CfgPtr, UINTPTR EffectiveAddress)
	Initialize the XDmaPcie instance provided by the caller based on the given Config structure. More...

void	XDmaPcie_GetVsecCapability (XDmaPcie InstancePtr, u8 VsecNum, u16 VsecIdPtr, u8 VersionPtr, u16 NextCapPtr)
	This API is used to read the VSEC Capability Register. More...

void	XDmaPcie_GetVsecHeader (XDmaPcie InstancePtr, u8 VsecNum, u16 VsecIdPtr, u8 RevisionPtr, u16 LengthPtr)
	This API is used to read the VSEC Header Register. More...

void	XDmaPcie_GetBridgeInfo (XDmaPcie InstancePtr, u8 Gen2Ptr, u8 RootPortPtr, u8 ECAMSizePtr)
	This API Reads the Bridge info register. More...

void	XDmaPcie_GetRequesterId (XDmaPcie InstancePtr, u8 BusNumPtr, u8 DevNumPtr, u8 FunNumPtr, u8 *PortNumPtr)
	Read the Bus Location register. More...

void	XDmaPcie_GetPhyStatusCtrl (XDmaPcie InstancePtr, u32 PhyState)
	This API is used to read the Phy Status/Control Register. More...

void	XDmaPcie_GetRootPortStatusCtrl (XDmaPcie InstancePtr, u32 StatusPtr)
	Read Root Port Status/Control Register. More...

void	XDmaPcie_SetRootPortStatusCtrl (XDmaPcie *InstancePtr, u32 StatusData)
	Write Value in Root Port Status/Control Register. More...

int	XDmaPcie_SetRootPortMSIBase (XDmaPcie *InstancePtr, unsigned long long MsiBase)
	Write MSI Base Address to Root Port MSI Base Address Register. More...

void	XDmaPcie_GetRootPortErrFIFOMsg (XDmaPcie InstancePtr, u16 ReqIdPtr, u8 ErrType, u8 ErrValid)
	Read Root Port Error FIFO Message. More...

void	XDmaPcie_ClearRootPortErrFIFOMsg (XDmaPcie *InstancePtr)
	Clear Root Port Error FIFO Message. More...

int	XDmaPcie_GetRootPortIntFIFOReg (XDmaPcie InstancePtr, u16 ReqIdPtr, u16 MsiAddr, u8 MsiInt, u8 IntValid, u16 MsiMsgData)
	Read Root Port Interrupt FIFO message Register 1 & 2. More...

void	XDmaPcie_ClearRootPortIntFIFOReg (XDmaPcie *InstancePtr)
	Clear Root Port FIFO Interrupt message Register 1 & 2. More...

void	XDmaPcie_GetLocalBusBar2PcieBar (XDmaPcie InstancePtr, u8 BarNumber, XDmaPcie_BarAddr BarAddrPtr)
	Read PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller. More...

void	XDmaPcie_SetLocalBusBar2PcieBar (XDmaPcie InstancePtr, u8 BarNumber, XDmaPcie_BarAddr BarAddrPtr)
	Write PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller. More...

void	XDmaPcie_ReadLocalConfigSpace (XDmaPcie InstancePtr, u16 Offset, u32 DataPtr)
	Read 32-bit value from one of this IP own configuration space. More...

void	XDmaPcie_WriteLocalConfigSpace (XDmaPcie *InstancePtr, u16 Offset, u32 Data)
	Write 32-bit value to one of this IP own configuration space. More...

void	XDmaPcie_ReadRemoteConfigSpace (XDmaPcie InstancePtr, u8 Bus, u8 Device, u8 Function, u16 Offset, u32 DataPtr)
	Read 32-bit value from external PCIe Function's configuration space. More...

void	XDmaPcie_WriteRemoteConfigSpace (XDmaPcie *InstancePtr, u8 Bus, u8 Device, u8 Function, u16 Offset, u32 Data)
	Write 32-bit value to external PCIe function's configuration space. More...

void	XDmaPcie_EnumerateFabric (XDmaPcie *XdmaPciePtr)
	This function starts PCIe enumeration. More...

void	XDmaPcie_EnableGlobalInterrupt (XDmaPcie *InstancePtr)
	Enable the Global Interrupt. More...

void	XDmaPcie_DisableGlobalInterrupt (XDmaPcie *InstancePtr)
	Disable the Global Interrupt. More...

void	XDmaPcie_EnableInterrupts (XDmaPcie *InstancePtr, u32 EnableMask)
	Enable the IP interrupt bits passed into "EnableMask". More...

void	XDmaPcie_DisableInterrupts (XDmaPcie *InstancePtr, u32 DisableMask)
	Disable the IP interrupt bits passed into "DisableMask". More...

void	XDmaPcie_GetEnabledInterrupts (XDmaPcie InstancePtr, u32 EnabledMaskPtr)
	Get the currently enabled interrupt bits of the IP and pass them back to the caller into "EnabledMask". More...

void	XDmaPcie_GetPendingInterrupts (XDmaPcie InstancePtr, u32 PendingMaskPtr)
	Get the currently pending interrupt bits of the IP and pass them back to the caller into "PendingMask". More...

void	XDmaPcie_ClearPendingInterrupts (XDmaPcie *InstancePtr, u32 ClearMask)
	Clear the currently pending interrupt bits of the IP passed from the caller into "ClearMask". More...

u8	XDmaPcie_HasCapability (XDmaPcie *InstancePtr, u8 Bus, u8 Device, u8 Function, u8 CapId)
	This function returns whether capability Id is available or not for the particular Function. More...

u64	XDmaPcie_GetCapability (XDmaPcie *InstancePtr, u8 Bus, u8 Device, u8 Function, u8 CapId)
	This function returns offset to the matching capability ID from the Function's Linked list of the capability registers. More...

u8	XDmaPcie_PrintAllCapabilites (XDmaPcie *InstancePtr, u8 Bus, u8 Device, u8 Function)
	This function prints all the available capabilities in the Function. More...

Macro Definition Documentation

#define MAX_BARS 6

No BAR allocation for Bridge.

#define REQ_SIZE (MAX_BARS * sizeof(unsigned long))

Required size for BAR Alignment.

#define XDmaPcie_IsEcamBusy ( InstancePtr )

Value:

(XDmaPcie_ReadReg((InstancePtr)->Config.BaseAddress, \

XDMAPCIE_BSC_OFFSET) & XDMAPCIE_BSC_ECAM_BUSY_MASK) ? TRUE : FALSE

XDMAPCIE_BSC_ECAM_BUSY_MASK

#define XDMAPCIE_BSC_ECAM_BUSY_MASK

ECAM Busy Status.

Definition: xdmapcie_hw.h:511

XDMAPCIE_BSC_OFFSET

#define XDMAPCIE_BSC_OFFSET

Bridge Status and Control Register.

Definition: xdmapcie_hw.h:220

XDmaPcie_ReadReg

#define XDmaPcie_ReadReg(BaseAddress, RegOffset)

Macro to read register.

Definition: xdmapcie_hw.h:972

Check whether ECAM is busy or not.

Parameters

InstancePtr is the XDmaPcie instance to operate on.

Returns

TRUE if ECAM is busy
FALSE if ECAM is idel

Note: This function is valid only when IP is configured as a root complex

Referenced by XDmaPcie_ReadRemoteConfigSpace(), and XDmaPcie_WriteRemoteConfigSpace().

#define XDmaPcie_IsLinkUp ( InstancePtr )

Value:

(XDmaPcie_ReadReg((InstancePtr)->Config.BaseAddress, \

XDMAPCIE_PHYSC_OFFSET) & XDMAPCIE_PHYSC_LINK_UP_MASK) ? TRUE : FALSE

XDMAPCIE_PHYSC_LINK_UP_MASK

#define XDMAPCIE_PHYSC_LINK_UP_MASK

Link Up Status Mask.

Definition: xdmapcie_hw.h:662

XDMAPCIE_PHYSC_OFFSET

#define XDMAPCIE_PHYSC_OFFSET

Physical status and Control Register.

Definition: xdmapcie_hw.h:246

XDmaPcie_ReadReg

#define XDmaPcie_ReadReg(BaseAddress, RegOffset)

Macro to read register.

Definition: xdmapcie_hw.h:972

Check whether link is up or not.

Parameters

InstancePtr is the XDmaPcie instance to operate on.

Returns

TRUE if link is up
FALSE if link is down

Note: None

Referenced by PcieInitRootComplex().

#define XDMAPCIE_VSEC1 0x00

First VSEC Register.

#define XDMAPCIE_VSEC2 0x01

Second VSEC Register.

Function Documentation

int XDmaPcie_CfgInitialize	(	XDmaPcie *	InstancePtr,
		XDmaPcie_Config *	CfgPtr,
		UINTPTR	EffectiveAddress
	)

Initialize the XDmaPcie instance provided by the caller based on the given Config structure.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.The memory of the pointer references must be pre-allocated by the caller.
CfgPtr	is the device configuration structure containing required HW build data.
EffectiveAddress	is the Physical address of the hardware in a Virtual Memory operating system environment.It is the Base Address in a stand alone environment.

Returns

            - XST_SUCCESS Initialization was successful.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::Ecam, XDmaPcie::IsReady, XDmaPcie::MaxNumOfBuses, XDmaPcie_Config::NpMemBaseAddr, XDMAPCIE_BI_ECAM_SIZE_MASK, XDMAPCIE_BI_ECAM_SIZE_SHIFT, XDMAPCIE_BI_OFFSET, XDmaPcie_DisableInterrupts(), XDMAPCIE_IM_DISABLE_ALL_MASK, and XDmaPcie_ReadReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_ClearPendingInterrupts	(	XDmaPcie *	InstancePtr,
		u32	ClearMask
	)

Clear the currently pending interrupt bits of the IP passed from the caller into "ClearMask".

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
ClearMask	is the bit pattern for pending interrupts wanted to be cleared.

Returns: None.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_ID_OFFSET, XDmaPcie_ReadReg, and XDmaPcie_WriteReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_ClearRootPortErrFIFOMsg ( XDmaPcie * InstancePtr )

Clear Root Port Error FIFO Message.

Parameters

InstancePtr is the PCIe component to operate on.

Returns: None.

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDMAPCIE_RPEFR_OFFSET, and XDmaPcie_WriteReg.

void XDmaPcie_ClearRootPortIntFIFOReg ( XDmaPcie * InstancePtr )

Clear Root Port FIFO Interrupt message Register 1 & 2.

Parameters

InstancePtr is the PCIe component to operate on

Returns: None.

Note: This function is valid only when IP is configured as a root complex.Clearing any one Interrupt FIFO register clears both registers.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDMAPCIE_RPIFR1_OFFSET, and XDmaPcie_WriteReg.

void XDmaPcie_DisableGlobalInterrupt ( XDmaPcie * InstancePtr )

Disable the Global Interrupt.

Parameters

InstancePtr is the XDmaPcie instance to operate on.

Returns: None

Note: This bit is in the Bridge Status and Control Register.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_BSC_GI_MASK, XDMAPCIE_BSC_GI_SHIFT, XDMAPCIE_BSC_OFFSET, XDmaPcie_ReadReg, and XDmaPcie_WriteReg.

void XDmaPcie_DisableInterrupts	(	XDmaPcie *	InstancePtr,
		u32	DisableMask
	)

Disable the IP interrupt bits passed into "DisableMask".

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
DisableMask	is the bit pattern for interrupts wanted to be disabled.

Returns: None

Note: If an interrupt is already disabled before calling this function, it will stay disabled regardless of the value of "DisableMask" passed from the caller.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_IM_OFFSET, XDmaPcie_ReadReg, and XDmaPcie_WriteReg.

Referenced by PcieInitRootComplex(), and XDmaPcie_CfgInitialize().

void XDmaPcie_EnableGlobalInterrupt ( XDmaPcie * InstancePtr )

Enable the Global Interrupt.

Parameters

InstancePtr is the XDmaPcie instance to operate on.

Returns: None

Note: This bit is in the Bridge Status and Control Register.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_BSC_GI_MASK, XDMAPCIE_BSC_GI_SHIFT, XDMAPCIE_BSC_OFFSET, XDmaPcie_ReadReg, and XDmaPcie_WriteReg.

void XDmaPcie_EnableInterrupts	(	XDmaPcie *	InstancePtr,
		u32	EnableMask
	)

Enable the IP interrupt bits passed into "EnableMask".

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
EnableMask	is the bit pattern for interrupts wanted to be enabled.

Returns: None

Note: If an interrupt is already enabled before calling this function, it will stay enabled regardless of the value of "EnableMask" passed from the caller.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_IM_OFFSET, XDmaPcie_ReadReg, and XDmaPcie_WriteReg.

void XDmaPcie_EnumerateFabric ( XDmaPcie * InstancePtr )

This function starts PCIe enumeration.

Parameters

InstancePtr pointer to XDmaPcie Instance Pointer

Returns: none

Referenced by main().

void XDmaPcie_GetBridgeInfo	(	XDmaPcie *	InstancePtr,
		u8 *	Gen2Ptr,
		u8 *	RootPortPtr,
		u8 *	ECAMSizePtr
	)

This API Reads the Bridge info register.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
Gen2Ptr	is a pointer to a variable indicating whether underlying PCIe block support PCIe Gen2 Speed.
RootPortPtr	is a pointer to a variable indication whether underlying PCIe block is root port.
ECAMSizePtr	is a pointer to a variable where it indicates ECAM size. Value is between 1 to 8. Total address bits dedicated to ECAM is 20 + ECAM size.

Returns: None.

Note: None

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_BI_ECAM_SIZE_MASK, XDMAPCIE_BI_ECAM_SIZE_SHIFT, XDMAPCIE_BI_GEN2_MASK, XDMAPCIE_BI_OFFSET, XDMAPCIE_BI_RP_MASK, XDMAPCIE_BI_RP_SHIFT, and XDmaPcie_ReadReg.

u64 XDmaPcie_GetCapability	(	XDmaPcie *	InstancePtr,
		u8	Bus,
		u8	Device,
		u8	Function,
		u8	CapId
	)

This function returns offset to the matching capability ID from the Function's Linked list of the capability registers.

Parameters

InstancePtr	pointer to XDmaPcie Instance Pointer
Bus	is the number of the Bus
Device	is the number of the Device
Function	is number of the Function
cap	id to get capability pointer offset

Returns: u64 capability pointer if available 0 if not available.

References XDmaPcie::Config, XDmaPcie_Config::Ecam, and XDmaPcie_ReadRemoteConfigSpace().

void XDmaPcie_GetEnabledInterrupts	(	XDmaPcie *	InstancePtr,
		u32 *	EnabledMaskPtr
	)

Get the currently enabled interrupt bits of the IP and pass them back to the caller into "EnabledMask".

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
EnabledMaskPtr	is a pointer to a variable where the driver will pass back the enabled interrupt bits after reading them from IP.

Returns: None.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_IM_OFFSET, and XDmaPcie_ReadReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_GetLocalBusBar2PcieBar	(	XDmaPcie *	InstancePtr,
		u8	BarNumber,
		XDmaPcie_BarAddr *	BarAddrPtr
	)

Read PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
BarNumber	is AXI bar number (0 - 5) passed by caller.
BarAddrPtr	is a pointer to a variable where the driver will . pass back translation vector.

Returns: None.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_BarAddr::LowerAddr, XDmaPcie_BarAddr::UpperAddr, XDMAPCIE_AXIBAR2PCIBAR_0L_OFFSET, XDMAPCIE_AXIBAR2PCIBAR_0U_OFFSET, and XDmaPcie_ReadReg.

void XDmaPcie_GetPendingInterrupts	(	XDmaPcie *	InstancePtr,
		u32 *	PendingMaskPtr
	)

Get the currently pending interrupt bits of the IP and pass them back to the caller into "PendingMask".

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
PendingMaskPtr	is a pointer to a variable where the driver will pass back the pending interrupt bits after reading them from IP.

Returns: None.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_ID_OFFSET, and XDmaPcie_ReadReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_GetPhyStatusCtrl	(	XDmaPcie *	InstancePtr,
		u32 *	PhyState
	)

This API is used to read the Phy Status/Control Register.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
PhyState	is a pointer to a variable where the driver will pass back Current physical status.

Returns: None.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_PHYSC_OFFSET, and XDmaPcie_ReadReg.

void XDmaPcie_GetRequesterId	(	XDmaPcie *	InstancePtr,
		u8 *	BusNumPtr,
		u8 *	DevNumPtr,
		u8 *	FunNumPtr,
		u8 *	PortNumPtr
	)

Read the Bus Location register.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
BusNumPtr	is a pointer to a variable where the driver will pass back the bus number of requester ID assigned to IP.
DevNumPtr	is a pointer to a variable where the driver will pass back the device number of requester ID assigned to IP.
FunNumPtr	is a pointer to a variable where the driver will pass back the function number of requester ID assigned to IP.
PortNumPtr	is a pointer to a variable where the driver will pass back the Port number of requester ID assigned to IP.

Returns: None.

Note: None

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_BL_BUS_MASK, XDMAPCIE_BL_BUS_SHIFT, XDMAPCIE_BL_DEV_MASK, XDMAPCIE_BL_DEV_SHIFT, XDMAPCIE_BL_FUNC_MASK, XDMAPCIE_BL_OFFSET, XDMAPCIE_BL_PORT_MASK, XDMAPCIE_BL_PORT_SHIFT, and XDmaPcie_ReadReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_GetRootPortErrFIFOMsg	(	XDmaPcie *	InstancePtr,
		u16 *	ReqIdPtr,
		u8 *	ErrType,
		u8 *	ErrValid
	)

Read Root Port Error FIFO Message.

Parameters

InstancePtr	is the PCIe component to operate on.
ReqIdPtr	is a variable where the driver will pass back the requester Id of error message.
ErrType	is a variable where the driver will pass back the type of error message
ErrValid	is a variable where the driver will pass back the status of read operation of error message.

Returns: None.

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDmaPcie_ReadReg, XDMAPCIE_RPEFR_ERR_TYPE_MASK, XDMAPCIE_RPEFR_ERR_TYPE_SHIFT, XDMAPCIE_RPEFR_ERR_VALID_MASK, XDMAPCIE_RPEFR_ERR_VALID_SHIFT, XDMAPCIE_RPEFR_OFFSET, and XDMAPCIE_RPEFR_REQ_ID_MASK.

int XDmaPcie_GetRootPortIntFIFOReg	(	XDmaPcie *	InstancePtr,
		u16 *	ReqIdPtr,
		u16 *	MsiAddr,
		u8 *	MsiInt,
		u8 *	IntValid,
		u16 *	MsiMsgData
	)

Read Root Port Interrupt FIFO message Register 1 & 2.

Parameters

InstancePtr	is the PCIe component to operate on.
ReqIdPtr	is a variable where the driver will pass back the requester Id of error message.
MsiAddr	is a variable where the driver will pass back the MSI address for which interrupt message received.
MsiInt	is a variable where the driver will pass back the type of interrupt message received (MSI/INTx).
IntValid	is a variable where the driver will pass back the status of read operation of interrupt message.
MsiMsgData	is a variable where the driver will pass back the MSI data received.

Returns: MsiMsgData if MSI interrupt is observed or 0 if there is no MSI interrupt.

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDmaPcie_ReadReg, XDMAPCIE_RPIFR1_INTR_VALID_MASK, XDMAPCIE_RPIFR1_INTR_VALID_SHIFT, XDMAPCIE_RPIFR1_MSI_ADDR_MASK, XDMAPCIE_RPIFR1_MSI_ADDR_SHIFT, XDMAPCIE_RPIFR1_MSIINTR_VALID_MASK, XDMAPCIE_RPIFR1_MSIINTR_VALID_SHIFT, XDMAPCIE_RPIFR1_OFFSET, XDMAPCIE_RPIFR1_REQ_ID_MASK, XDMAPCIE_RPIFR2_MSG_DATA_MASK, and XDMAPCIE_RPIFR2_OFFSET.

void XDmaPcie_GetRootPortStatusCtrl	(	XDmaPcie *	InstancePtr,
		u32 *	StatusPtr
	)

Read Root Port Status/Control Register.

Parameters

InstancePtr	is the PCIe component to operate on.
StatusPtr	is a pointer to a variable where the driver will pass back the root port status.

Returns: None.

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDmaPcie_ReadReg, and XDMAPCIE_RPSC_OFFSET.

void XDmaPcie_GetVsecCapability	(	XDmaPcie *	InstancePtr,
		u8	VsecNum,
		u16 *	VsecIdPtr,
		u8 *	VersionPtr,
		u16 *	NextCapPtr
	)

This API is used to read the VSEC Capability Register.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
VsecNum	is a VSEC register number as there are two registers. Possible values are. XDMAPCIE_VSEC1 (0) XDMAPCIE_VSEC2 (1)
VsecIdPtr	is a pointer to a variable where the driver will pass back the Vendor Specific Enhanced Capability ID.
VersionPtr	is a pointer to a variable where the driver will . pass back the Version of VSEC.
NextCapPtr	is a pointer to a variable where the driver will pass back the Next Capability offset.

Returns: None.

Note: None

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDmaPcie_ReadReg, XDMAPCIE_VSECC_ID_MASK, XDMAPCIE_VSECC_NEXT_MASK, XDMAPCIE_VSECC_NEXT_SHIFT, XDMAPCIE_VSECC_OFFSET, XDMAPCIE_VSECC_VER_MASK, and XDMAPCIE_VSECC_VER_SHIFT.

void XDmaPcie_GetVsecHeader	(	XDmaPcie *	InstancePtr,
		u8	VsecNum,
		u16 *	VsecIdPtr,
		u8 *	RevisionPtr,
		u16 *	LengthPtr
	)

This API is used to read the VSEC Header Register.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
VsecNum	is a VSEC register number as there are two registers. Possible values are. XDMAPCIE_VSEC1 (0) XDMAPCIE_VSEC2 (1)
VsecIdPtr	is a pointer to a variable where the driver will pass back the VSEC header structure Id.
RevisionPtr	is a pointer to a variable where the driver will pass back the Revision of VSEC capability Structure.
LengthPtr	is a pointer to a variable where the driver will pass . back the length of the VSEC capability structure.

Returns: None.

Note: None

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDmaPcie_ReadReg, XDMAPCIE_VSECH_ID_MASK, XDMAPCIE_VSECH_LEN_MASK, XDMAPCIE_VSECH_LEN_SHIFT, XDMAPCIE_VSECH_OFFSET, XDMAPCIE_VSECH_REV_MASK, and XDMAPCIE_VSECH_REV_SHIFT.

u8 XDmaPcie_HasCapability	(	XDmaPcie *	InstancePtr,
		u8	Bus,
		u8	Device,
		u8	Function,
		u8	CapId
	)

This function returns whether capability Id is available or not for the particular Function.

Parameters

InstancePtr	pointer to XDmaPcie Instance Pointer
Bus	is the number of the Bus
Device	is the number of the Device
Function	is number of the Function
cap	id to check capability pointer availability

Returns: u32 0 if capability is not available 1 if capability is available

References XDmaPcie_ReadRemoteConfigSpace().

XDmaPcie_Config* XDmaPcie_LookupConfig ( u16 DeviceId )

Lookup the device configuration based on the unique device ID.

The table ConfigTable contains the configuration info for each device in the system.

Parameters

DeviceId is the device identifier to lookup.

Returns

XDmaPcie configuration structure pointer if DeviceID is found.
NULL if DeviceID is not found.

Note: None

Referenced by PcieInitRootComplex().

u8 XDmaPcie_PrintAllCapabilites	(	XDmaPcie *	InstancePtr,
		u8	Bus,
		u8	Device,
		u8	Function
	)

This function prints all the available capabilities in the Function.

Parameters

InstancePtr	pointer to XDmaPcie Instance Pointer
Bus	is the number of the Bus
Device	is the number of the Device
Function	is number of the Function

Returns: XST_SUCCESS on success XST_FAILURE on failure.

References XDmaPcie_ReadRemoteConfigSpace().

void XDmaPcie_ReadLocalConfigSpace	(	XDmaPcie *	InstancePtr,
		u16	Offset,
		u32 *	DataPtr
	)

Read 32-bit value from one of this IP own configuration space.

Location is identified by its offset from the beginning of the configuration space.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
Offset	from beginning of IP own configuration space.
DataPtr	is a pointer to a variable where the driver will pass back the value read from the specified location.

Returns: None

Note: None

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie::IsReady, XDMAPCIE_PCIE_CORE_OFFSET, and XDmaPcie_ReadReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_ReadRemoteConfigSpace	(	XDmaPcie *	InstancePtr,
		u8	Bus,
		u8	Device,
		u8	Function,
		u16	Offset,
		u32 *	DataPtr
	)

Read 32-bit value from external PCIe Function's configuration space.

External PCIe function is identified by its Requester ID (Bus#, Device#, Function#). Location is identified by its offset from the beginning of the configuration space.

Parameters

InstancePtr	is the PCIe component to operate on.
Bus	is the external PCIe function's Bus number.
Device	is the external PCIe function's Device number.
Function	is the external PCIe function's Function number.
Offset	from beggininng of PCIe function's configuration space.
DataPtr	is a pointer to a variable where the driver will pass back the value read from the specified location.

Returns: None

Note: This function is valid only when IP is configured as a root complex. The XDmaPcie_ReadLocalConfigSpace API should be used for reading the local config space.

References XDmaPcie::Config, XDmaPcie_Config::Ecam, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDmaPcie::MaxNumOfBuses, XDMAPCIE_ATU_LIMIT_ADDR, XDMAPCIE_ATU_REGION_SIZE, XDMAPCIE_CFG_TLP_TYPE0, XDMAPCIE_CFG_TLP_TYPE1, XDmaPcie_IsEcamBusy, XDmaPcie_ReadReg, and XDMAPCIE_REGION_EN.

Referenced by XDmaPcie_GetCapability(), XDmaPcie_HasCapability(), and XDmaPcie_PrintAllCapabilites().

void XDmaPcie_SetLocalBusBar2PcieBar	(	XDmaPcie *	InstancePtr,
		u8	BarNumber,
		XDmaPcie_BarAddr *	BarAddrPtr
	)

Write PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller.

Parameters

InstancePtr	is the XDmaPcie instance to operate on.
BarNumber	is AXI bar number (0 - 5) passed by caller.
BarAddrPtr	is a pointer to a variable where the driver will pass back translation vector.

Returns: None.

Note: None.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_BarAddr::LowerAddr, XDmaPcie_BarAddr::UpperAddr, XDMAPCIE_AXIBAR2PCIBAR_0L_OFFSET, XDMAPCIE_AXIBAR2PCIBAR_0U_OFFSET, and XDmaPcie_WriteReg.

int XDmaPcie_SetRootPortMSIBase	(	XDmaPcie *	InstancePtr,
		unsigned long long	MsiBase
	)

Write MSI Base Address to Root Port MSI Base Address Register.

Parameters

InstancePtr	is the PCIe component to operate on.
MsiBase	is 64 bit base address for MSI.This address should be 4kB aligned always.

Returns: XST_SUCCESS if success or XST_FAILURE if failure .

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDMAPCIE_RPMSIB_LOWER_MASK, XDMAPCIE_RPMSIB_LOWER_OFFSET, XDMAPCIE_RPMSIB_UPPER_MASK, XDMAPCIE_RPMSIB_UPPER_OFFSET, and XDmaPcie_WriteReg.

void XDmaPcie_SetRootPortStatusCtrl	(	XDmaPcie *	InstancePtr,
		u32	StatusData
	)

Write Value in Root Port Status/Control Register.

Parameters

InstancePtr	is the PCIe component to operate on.
StatusData	is data to set.

Returns: None.

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDMAPCIE_RPSC_MASK, XDMAPCIE_RPSC_OFFSET, and XDmaPcie_WriteReg.

void XDmaPcie_WriteLocalConfigSpace	(	XDmaPcie *	InstancePtr,
		u16	Offset,
		u32	Data
	)

Write 32-bit value to one of this IP own configuration space.

Location is identified by its offset from the beginning of the configuration space.

Parameters

InstancePtr	is the PCIe component to operate on.
Offset	from beggininng of IP own configuration space.
Data	to be written to the specified location.

Returns: None

Note: This function is valid only when IP is configured as a root complex.

References XDmaPcie_Config::BaseAddress, XDmaPcie::Config, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDMAPCIE_PCIE_CORE_OFFSET, and XDmaPcie_WriteReg.

Referenced by PcieInitRootComplex().

void XDmaPcie_WriteRemoteConfigSpace	(	XDmaPcie *	InstancePtr,
		u8	Bus,
		u8	Device,
		u8	Function,
		u16	Offset,
		u32	Data
	)

Write 32-bit value to external PCIe function's configuration space.

External PCIe function is identified by its Requester ID (Bus#, Device#, Function#). Location is identified by its offset from the beginning of the configuration space.

Parameters

InstancePtr	is the PCIe component to operate on.
Bus	is the external PCIe function's Bus number.
Device	is the external PCIe function's Device number.
Function	is the external PCIe function's Function number.
Offset	from beggininng of PCIe function's configuration space.
Data	to be written to the specified location.

Returns: None

Note: This function is valid only when IP is configured as a root complex. The XDmaPcie_WriteLocalConfigSpace should be used for writing to local config space.

References XDmaPcie::Config, XDmaPcie_Config::Ecam, XDmaPcie_Config::IncludeRootComplex, XDmaPcie::IsReady, XDmaPcie::MaxNumOfBuses, XDmaPcie_IsEcamBusy, XDmaPcie_ReadReg, and XDmaPcie_WriteReg.

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