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v_hdmitx1
Vitis Drivers API Documentation
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v_hdmitx1
Vitis Drivers API Documentation
|
This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx HDMI TX core.
For more information about the operation of this core see the hardware specification and documentation in the higher level driver xv_hdmitx1.h file.
MODIFICATION HISTORY:
Ver Who Date Changes
1.00 EB 22/05/18 Initial release.
Macros | |
| #define | XV_HDMITX1_HW_H_ |
| Prevent circular inclusions by using protection macros. More... | |
| #define | XV_HDMITX1_DDC_SINK_VER_REG 0x01 |
| < DDC Register Address More... | |
| #define | XV_HDMITX1_DDC_CFG_1_FRL_RATE_MASK 0xF |
| VER (Version Interface) peripheral register offsets. More... | |
| #define | XV_HDMITX1_VER_ID_OFFSET ((XV_HDMITX1_VER_BASE)+(0*4)) |
| VER Identification * Register offset. More... | |
| #define | XV_HDMITX1_VER_VERSION_OFFSET ((XV_HDMITX1_VER_BASE)+(1*4)) |
| VER Version Register * offset. More... | |
| #define | XV_HDMITX1_BRDG_FIFO_LVL_OFFSET ((XV_HDMITX1_VER_BASE)+(2*4)) |
| Bridge FIFO Level Register offset. More... | |
| #define | XV_HDMITX1_VCKE_SYS_CNT_OFFSET ((XV_HDMITX1_VER_BASE)+(3*4)) |
| VCKE System Count Register offset. More... | |
| #define | XV_HDMITX1_DBG_STS_OFFSET ((XV_HDMITX1_VER_BASE)+(4*4)) |
| Debug Status Register offset. More... | |
| #define | XV_HDMITX1_ANLZ_HBP_HS_OFFSET ((XV_HDMITX1_VER_BASE)+(5*4)) |
| Analyzer HPB HS Register offset. More... | |
| #define | XV_HDMITX1_ANLZ_LN_ACT_OFFSET ((XV_HDMITX1_VER_BASE)+(6*4)) |
| Analyzer LN ACT Register offset. More... | |
| #define | XV_HDMITX1_BRDG_FIFO_LVL_MIN_MASK 0xFFFF |
| FRL Control Lane 0 LTP mask. More... | |
| #define | XV_HDMITX1_BRDG_FIFO_LVL_MIN_SHIFT 0 |
| FRL Control Lane 0 LTP shift. More... | |
| #define | XV_HDMITX1_BRDG_FIFO_LVL_MAX_MASK 0xFFFF |
| FRL Control Lane 0 LTP mask. More... | |
| #define | XV_HDMITX1_BRDG_FIFO_LVL_MAX_SHIFT 16 |
| FRL Control Lane 0 LTP shift. More... | |
| #define | XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_SHIFT 0 |
| Analyzer hsync size shift. More... | |
| #define | XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_MASK 0xFFFF |
| Analyzer hsync size mask. More... | |
| #define | XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_SHIFT 16 |
| Analyzer hbp size shift. More... | |
| #define | XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_MASK 0xFFFF |
| Analyzer hbp size mask. More... | |
| #define | XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_SHIFT 0 |
| Analyzer analyzer act size shift. More... | |
| #define | XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_MASK 0xFFFF |
| Analyzer analyzer act size mask. More... | |
| #define | XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_SHIFT 16 |
| Analyzer analyzer line act shift. More... | |
| #define | XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_MASK 0xFFFF |
| Analyzer analyzer line act mask. More... | |
| #define | XV_HDMITX1_PIO_ID_OFFSET ((XV_HDMITX1_PIO_BASE)+(0*4)) |
| PIO Identification * Register offset. More... | |
| #define | XV_HDMITX1_PIO_CTRL_OFFSET ((XV_HDMITX1_PIO_BASE)+(1*4)) |
| PIO Control Register * offset. More... | |
| #define | XV_HDMITX1_PIO_CTRL_SET_OFFSET ((XV_HDMITX1_PIO_BASE)+(2*4)) |
| PIO Control Register Set * offset. More... | |
| #define | XV_HDMITX1_PIO_CTRL_CLR_OFFSET ((XV_HDMITX1_PIO_BASE)+(3*4)) |
| PIO Control Register Clear * offset. More... | |
| #define | XV_HDMITX1_PIO_STA_OFFSET ((XV_HDMITX1_PIO_BASE)+(4*4)) |
| PIO Status Register * offset. More... | |
| #define | XV_HDMITX1_PIO_OUT_OFFSET ((XV_HDMITX1_PIO_BASE)+(5*4)) |
| PIO Out Register offset. More... | |
| #define | XV_HDMITX1_PIO_OUT_SET_OFFSET ((XV_HDMITX1_PIO_BASE)+(6*4)) |
| PIO Out Register Set * offset. More... | |
| #define | XV_HDMITX1_PIO_OUT_CLR_OFFSET ((XV_HDMITX1_PIO_BASE)+(7*4)) |
| PIO Out Register Clear * offset. More... | |
| #define | XV_HDMITX1_PIO_OUT_MSK_OFFSET ((XV_HDMITX1_PIO_BASE)+(8*4)) |
| PIO Out Mask Register * offset. More... | |
| #define | XV_HDMITX1_PIO_IN_OFFSET ((XV_HDMITX1_PIO_BASE)+(9*4)) |
| PIO In Register offset. More... | |
| #define | XV_HDMITX1_PIO_IN_EVT_OFFSET ((XV_HDMITX1_PIO_BASE)+(10*4)) |
| PIO In Event Register * offset. More... | |
| #define | XV_HDMITX1_PIO_IN_EVT_RE_OFFSET ((XV_HDMITX1_PIO_BASE)+(11*4)) |
| PIO In Event Rising Edge Register offset. More... | |
| #define | XV_HDMITX1_PIO_IN_EVT_FE_OFFSET ((XV_HDMITX1_PIO_BASE)+(12*4)) |
| PIO In Event Falling Edge Register offset. More... | |
| #define | XV_HDMITX1_HPD_TIMEGRID_OFFSET ((XV_HDMITX1_PIO_BASE)+(13*4)) |
| PIO HPD Config. More... | |
| #define | XV_HDMITX1_TOGGLE_CONF_OFFSET ((XV_HDMITX1_PIO_BASE)+(14*4)) |
| PIO HPD Config. More... | |
| #define | XV_HDMITX1_CONNECT_CONF_OFFSET ((XV_HDMITX1_PIO_BASE)+(15*4)) |
| PIO HPD Config. More... | |
| #define | XV_HDMITX1_PIO_CTRL_RUN_MASK (1<<0) |
| PIO Control Run mask. More... | |
| #define | XV_HDMITX1_PIO_CTRL_IE_MASK (1<<1) |
| PIO Control Interrupt Enable mask. More... | |
| #define | XV_HDMITX1_PIO_STA_IRQ_MASK (1<<0) |
| PIO Status Interrupt mask. More... | |
| #define | XV_HDMITX1_PIO_STA_EVT_MASK (1<<1) |
| PIO Status Event mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_RST_MASK (1<<0) |
| PIO Out Reset mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_MODE_MASK (1<<3) |
| PIO Out Mode mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_COLOR_DEPTH_MASK 0x30 |
| PIO Out Color Depth mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_PIXEL_RATE_MASK 0xC0 |
| PIO Out Pixel Rate mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_SAMPLE_RATE_MASK 0x300 |
| PIO Out Sample Rate mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_COLOR_SPACE_MASK 0xC00 |
| PIO Out Color Space mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_SCRM_MASK (1<<12) |
| PIO Out Scrambler mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_COLOR_DEPTH_SHIFT 4 |
| PIO Out Color Depth shift. More... | |
| #define | XV_HDMITX1_PIO_OUT_PIXEL_RATE_SHIFT 6 |
| PIO Out Pixel Rate shift. More... | |
| #define | XV_HDMITX1_PIO_OUT_SAMPLE_RATE_SHIFT 8 |
| PIO Out Sample Rate shift. More... | |
| #define | XV_HDMITX1_PIO_OUT_COLOR_SPACE_SHIFT 10 |
| PIO Out Color Space shift. More... | |
| #define | XV_HDMITX1_PIO_OUT_GCP_CLEARAVMUTE_MASK (1<<28) |
| PIO Out GCP_CLEARAVMUTE mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK (1<<29) |
| PIO Out Bridge_YUV420 mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK (1<<30) |
| PIO Out Bridge_Pixel repeat mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_GCP_AVMUTE_MASK (1<<31) |
| PIO Out GCP_AVMUTE mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_INT_VRST_MASK (1<<0) |
| PIO Out INT_VRST mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_INT_LRST_MASK (1<<20) |
| PIO Out INT_LRST mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_EXT_VRST_MASK (1<<21) |
| PIO Out EXT_VRST mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_EXT_SYSRST_MASK (1<<22) |
| PIO Out EXT_SYSRST mask. More... | |
| #define | XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK (1 << 23) |
| PIO Out Dynamic HDR Data Mover Enable. More... | |
| #define | XV_HDMITX1_PIO_IN_LNK_RDY_MASK (1<<0) |
| PIO In link ready mask. More... | |
| #define | XV_HDMITX1_PIO_IN_VID_RDY_MASK (1<<1) |
| PIO In video ready mask. More... | |
| #define | XV_HDMITX1_PIO_IN_HPD_MASK (1<<2) |
| PIO In HPD mask. More... | |
| #define | XV_HDMITX1_PIO_IN_VS_MASK (1<<3) |
| PIO In Vsync mask. More... | |
| #define | XV_HDMITX1_PIO_IN_PPP_MASK 0x07 |
| PIO In Pixel packing phase mask. More... | |
| #define | XV_HDMITX1_PIO_IN_HPD_TOGGLE_MASK (1<<8) |
| PIO In HPD toggle mask. More... | |
| #define | XV_HDMITX1_PIO_IN_PPP_SHIFT 5 |
| PIO In Pixel packing phase shift. More... | |
| #define | XV_HDMITX1_PIO_IN_BRDG_LOCKED_MASK (1<<9) |
| PIO In Bridge Locked mask. More... | |
| #define | XV_HDMITX1_PIO_IN_BRDG_OVERFLOW_MASK (1<<10) |
| PIO In Bridge Overflow mask. More... | |
| #define | XV_HDMITX1_PIO_IN_BRDG_UNDERFLOW_MASK (1<<11) |
| PIO In Bridge Underflow mask. More... | |
| #define | XV_HDMITX1_DDC_ID_OFFSET ((XV_HDMITX1_DDC_BASE)+(0*4)) |
| DDC Identification * Register offset. More... | |
| #define | XV_HDMITX1_DDC_CTRL_OFFSET ((XV_HDMITX1_DDC_BASE)+(1*4)) |
| DDC Control Register * offset. More... | |
| #define | XV_HDMITX1_DDC_CTRL_SET_OFFSET ((XV_HDMITX1_DDC_BASE)+(2*4)) |
| DDC Control Register Set * offset. More... | |
| #define | XV_HDMITX1_DDC_CTRL_CLR_OFFSET ((XV_HDMITX1_DDC_BASE)+(3*4)) |
| DDC Control Register Clear * offset. More... | |
| #define | XV_HDMITX1_DDC_STA_OFFSET ((XV_HDMITX1_DDC_BASE)+(4*4)) |
| DDC Status Register * offset. More... | |
| #define | XV_HDMITX1_DDC_CMD_OFFSET ((XV_HDMITX1_DDC_BASE)+(5*4)) |
| DDC Command Register * offset. More... | |
| #define | XV_HDMITX1_DDC_DAT_OFFSET ((XV_HDMITX1_DDC_BASE)+(6*4)) |
| DDC Data Register * offset. More... | |
| #define | XV_HDMITX1_DDC_CTRL_RUN_MASK (1<<0) |
| DDC Control Run mask. More... | |
| #define | XV_HDMITX1_DDC_CTRL_IE_MASK (1<<1) |
| DDC Control Interrupt Enable mask. More... | |
| #define | XV_HDMITX1_DDC_CTRL_TO_STOP_MASK (1<<2) |
| DDC Control TO Stop mask. More... | |
| #define | XV_HDMITX1_DDC_CTRL_CLK_DIV_MASK 0xFFFF |
| DDC Control Clock Divider mask. More... | |
| #define | XV_HDMITX1_DDC_STA_IRQ_MASK (1<<0) |
| DDC Status IRQ mask. More... | |
| #define | XV_HDMITX1_DDC_STA_EVT_MASK (1<<1) |
| DDC Status Event mask. More... | |
| #define | XV_HDMITX1_DDC_STA_BUSY_MASK (1<<2) |
| DDC Status Busy mask. More... | |
| #define | XV_HDMITX1_DDC_STA_DONE_MASK (1<<3) |
| DDC Status Busy mask. More... | |
| #define | XV_HDMITX1_DDC_STA_TIMEOUT_MASK (1<<4) |
| DDC Status Timeout mask. More... | |
| #define | XV_HDMITX1_DDC_STA_ACK_MASK (1<<5) |
| DDC Status ACK mask. More... | |
| #define | XV_HDMITX1_DDC_STA_SCL_MASK (1<<6) |
| DDC State of SCL Input mask. More... | |
| #define | XV_HDMITX1_DDC_STA_SDA_MASK (1<<7) |
| DDC State of SDA Input mask. More... | |
| #define | XV_HDMITX1_DDC_STA_CMD_FULL (1<<8) |
| Command fifo full. More... | |
| #define | XV_HDMITX1_DDC_STA_DAT_EMPTY (1<<9) |
| Data fifo empty. More... | |
| #define | XV_HDMITX1_DDC_STA_CMD_WRDS_MASK 0xFF |
| Command fifo words mask. More... | |
| #define | XV_HDMITX1_DDC_STA_CMD_WRDS_SHIFT 16 |
| Command fifo words shift. More... | |
| #define | XV_HDMITX1_DDC_STA_DAT_WRDS_MASK 0xFF |
| Data fifo words mask. More... | |
| #define | XV_HDMITX1_DDC_STA_DAT_WRDS_SHIFT 24 |
| Data fifo words shift. More... | |
| #define | XV_HDMITX1_DDC_CMD_STR_TOKEN (0x100) |
| Start token. More... | |
| #define | XV_HDMITX1_DDC_CMD_STP_TOKEN (0x101) |
| Stop token. More... | |
| #define | XV_HDMITX1_DDC_CMD_RD_TOKEN (0x102) |
| Read token. More... | |
| #define | XV_HDMITX1_DDC_CMD_WR_TOKEN (0x103) |
| Write token. More... | |
| #define | XV_HDMITX1_AUX_ID_OFFSET ((XV_HDMITX1_AUX_BASE)+(0*4)) |
| AUX Identification * Register offset. More... | |
| #define | XV_HDMITX1_AUX_CTRL_OFFSET ((XV_HDMITX1_AUX_BASE)+(1*4)) |
| AUX Control Register * offset. More... | |
| #define | XV_HDMITX1_AUX_CTRL_SET_OFFSET ((XV_HDMITX1_AUX_BASE)+(2*4)) |
| AUX Control Register Set * offset. More... | |
| #define | XV_HDMITX1_AUX_CTRL_CLR_OFFSET ((XV_HDMITX1_AUX_BASE)+(3*4)) |
| AUX Control Register Clear * offset. More... | |
| #define | XV_HDMITX1_AUX_STA_OFFSET ((XV_HDMITX1_AUX_BASE)+(4*4)) |
| AUX Status Register * offset. More... | |
| #define | XV_HDMITX1_AUX_DAT_OFFSET ((XV_HDMITX1_AUX_BASE)+(5*4)) |
| AUX Data Register * offset. More... | |
| #define | XV_HDMITX1_AUX_VTEM_OFFSET ((XV_HDMITX1_AUX_BASE)+(6*4)) |
| AUX VTEM Register offset. More... | |
| #define | XV_HDMITX1_AUX_FSYNC_OFFSET ((XV_HDMITX1_AUX_BASE)+(7*4)) |
| AUX FSYNC Register offset. More... | |
| #define | XV_HDMITX1_AUX_FSYNC_PRO_OF ((XV_HDMITX1_AUX_BASE)+(8*4)) |
| AUX FYNC PRO Register offset. More... | |
| #define | XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET (XV_HDMITX1_AUX_BASE + (9 * 4)) |
| AUX Dynamic HDR Packet offset. More... | |
| #define | XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET (XV_HDMITX1_AUX_BASE + (10 * 4)) |
| AUX Dynamic HDR Address LSB offset. More... | |
| #define | XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET (XV_HDMITX1_AUX_BASE + (11 * 4)) |
| AUX Dynamic HDR Address MSB offset. More... | |
| #define | XV_HDMITX1_AUX_CTRL_RUN_MASK (1<<0) |
| AUX Control Run mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_IE_MASK (1<<1) |
| AUX Control Interrupt Enable mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_VRR_EN_MASK (1<<2) |
| AUX Control VRR En mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK (1<<3) |
| AUX Control FSync En mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK (1 << 4) |
| AUX Control Enable Dynamic HDR mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK (1 << 5) |
| AUX Control Enable Graphic Overlay Flag mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK (1 << 6) |
| AUX Control Graphic Overlay Flag value mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK (1 << 7) |
| AUX Control FAPA Location value mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_DSC_EN_MASK (1<<8) |
| AUX Control DSC En mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_SYNC_EN_MASK (1<<9) |
| AUX Control SYNC En mask. More... | |
| #define | XV_HDMITX1_AUX_CTRL_DATASET_LEN_EN_MASK (1<<10) |
| AUX Control Data Set Length En mask. More... | |
| #define | XV_HDMITX1_AUX_STA_IRQ_MASK (1<<0) |
| AUX Status Interrupt mask. More... | |
| #define | XV_HDMITX1_AUX_STA_FIFO_EMT_MASK (1<<1) |
| AUX Status FIFO Empty mask. More... | |
| #define | XV_HDMITX1_AUX_STA_FIFO_FUL_MASK (1<<2) |
| AUX Status FIFO Full mask. More... | |
| #define | XV_HDMITX1_AUX_STA_PKT_RDY_MASK (1<<3) |
| AUX Status FIFO Ready mask. More... | |
| #define | XV_HDMITX1_AUX_STA_FREE_PKTS_MASK 0x0F |
| AUX Status Free Packets mask. More... | |
| #define | XV_HDMITX1_AUX_STA_FREE_PKTS_SHIFT 15 |
| AUX Status Free Packets shift. More... | |
| #define | XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK (1 << 8) |
| AUX Status Dynamic HDR MTW started. More... | |
| #define | XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK (1 << 9) |
| AUX Status Dynamic HDR read response. More... | |
| #define | XV_HDMITX1_AUX_STA_DSC_PKT_WRRDY_MASK (1 << 10) |
| AUX Status DSC Packet Write Ready. More... | |
| #define | XV_HDMITX1_AUD_ID_OFFSET ((XV_HDMITX1_AUD_BASE)+(0*4)) |
| AUD Identification * Register offset. More... | |
| #define | XV_HDMITX1_AUD_CTRL_OFFSET ((XV_HDMITX1_AUD_BASE)+(1*4)) |
| AUD Control Register * offset. More... | |
| #define | XV_HDMITX1_AUD_CTRL_SET_OFFSET ((XV_HDMITX1_AUD_BASE)+(2*4)) |
| AUD Control Register Set * offset. More... | |
| #define | XV_HDMITX1_AUD_CTRL_CLR_OFFSET ((XV_HDMITX1_AUD_BASE)+(3*4)) |
| AUD Control Register Clear * offset. More... | |
| #define | XV_HDMITX1_AUD_STA_OFFSET ((XV_HDMITX1_AUD_BASE)+(4*4)) |
| AUD Status Register * offset. More... | |
| #define | XV_HDMITX1_AUD_ACR_N_OFFSET ((XV_HDMITX1_AUD_BASE)+(5*4)) |
| AUD Clock Regeneration CTS * Register offset. More... | |
| #define | XV_HDMITX1_AUD_ACR_CTS_OFFSET ((XV_HDMITX1_AUD_BASE)+(6*4)) |
| AUD Clock Regeneration N * Register offset. More... | |
| #define | XV_HDMITX1_AUD_CTRL_RUN_MASK (1<<0) |
| AUD Control Run mask. More... | |
| #define | XV_HDMITX1_AUD_CTRL_IE_MASK (1<<1) |
| AUD Control Interrupt Enable mask. More... | |
| #define | XV_HDMITX1_AUD_CTRL_CH_MASK 0x03 |
| AUD Control channels mask. More... | |
| #define | XV_HDMITX1_AUD_CTRL_CH_SHIFT 2 |
| AUD Control channels mask. More... | |
| #define | XV_HDMITX1_3DAUD_CTRL_CH_MASK 0x07 |
| 3D AUD Control channels mask More... | |
| #define | XV_HDMITX1_3DAUD_CTRL_CH_SHIFT 18 |
| 3D AUD Control channels mask More... | |
| #define | XV_HDMITX1_AUD_CTRL_AUDFMT_MASK (1<<4) |
| AUD Control AUD Format mask. More... | |
| #define | XV_HDMITX1_AUD_CTRL_AUDFMT_SHIFT 4 |
| AUD Control AUD Format shift. More... | |
| #define | XV_HDMITX1_AUD_CTRL_3DAUDFMT_MASK (0x3 << 16) |
| 3D AUD Control AUD Format mask More... | |
| #define | XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT 16 |
| 3DAUD Control AUD Format Format shift More... | |
| #define | XV_HDMITX1_AUD_CTRL_3DAUDFMT_EN (0x1 << XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT) |
| 3DAUD en More... | |
| #define | XV_HDMITX1_AUD_STA_IRQ_MASK (1<<0) |
| AUD Status Interrupt mask. More... | |
| #define | XV_HDMITX1_AUD_ACR_N_MASK 0xFFFFF |
| AUD ACR N mask. More... | |
| #define | XV_HDMITX1_AUD_ACR_CTS_MASK 0xFFFFF |
| AUD ACR CTS mask. More... | |
| #define | XV_HDMITX1_AUD_ACR_CTS_VLD_MASK (1<<31) |
| AUD ACR CTS Valid mask. More... | |
| #define | XV_HDMITX1_MASK_ID_OFFSET ((XV_HDMITX1_MASK_BASE)+(0*4)) |
| MASK Identification Register offset. More... | |
| #define | XV_HDMITX1_MASK_CTRL_OFFSET ((XV_HDMITX1_MASK_BASE)+(1*4)) |
| MASK Control Register offset. More... | |
| #define | XV_HDMITX1_MASK_CTRL_SET_OFFSET ((XV_HDMITX1_MASK_BASE)+(2*4)) |
| MASK Control Register Set offset. More... | |
| #define | XV_HDMITX1_MASK_CTRL_CLR_OFFSET ((XV_HDMITX1_MASK_BASE)+(3*4)) |
| MASK Control Register Clear offset. More... | |
| #define | XV_HDMITX1_MASK_STA_OFFSET ((XV_HDMITX1_MASK_BASE)+(4*4)) |
| MASK Status Register offset. More... | |
| #define | XV_HDMITX1_MASK_RED_OFFSET ((XV_HDMITX1_MASK_BASE)+(5*4)) |
| MASK Red Component Register offset. More... | |
| #define | XV_HDMITX1_MASK_GREEN_OFFSET ((XV_HDMITX1_MASK_BASE)+(6*4)) |
| MASK Green Component Register offset. More... | |
| #define | XV_HDMITX1_MASK_BLUE_OFFSET ((XV_HDMITX1_MASK_BASE)+(7*4)) |
| MASK Blue Component Register offset. More... | |
| #define | XV_HDMITX1_MASK_CTRL_RUN_MASK (1<<0) |
| MASK Control Run mask. More... | |
| #define | XV_HDMITX1_MASK_CTRL_NOISE_MASK (1<<2) |
| MASK Control Noise. More... | |
| #define | XV_HDMITX1_FRL_ID_OFFSET ((XV_HDMITX1_FRL_BASE)+(0*4)) |
| FRL Identification Register offset. More... | |
| #define | XV_HDMITX1_FRL_CTRL_OFFSET ((XV_HDMITX1_FRL_BASE)+(1*4)) |
| FRL Control Register offset. More... | |
| #define | XV_HDMITX1_FRL_CTRL_SET_OFFSET ((XV_HDMITX1_FRL_BASE)+(2*4)) |
| FRL Control Register Set offset. More... | |
| #define | XV_HDMITX1_FRL_CTRL_CLR_OFFSET ((XV_HDMITX1_FRL_BASE)+(3*4)) |
| FRL Control Register Clear offset. More... | |
| #define | XV_HDMITX1_FRL_STA_OFFSET ((XV_HDMITX1_FRL_BASE)+(4*4)) |
| FRL Status Register offset. More... | |
| #define | XV_HDMITX1_FRL_TMR_OFFSET ((XV_HDMITX1_FRL_BASE)+(5*4)) |
| FRL Timer Register offset. More... | |
| #define | XV_HDMITX1_FRL_LNK_CLK_OFFSET ((XV_HDMITX1_FRL_BASE)+(6*4)) |
| FRL Link Clock Register offset. More... | |
| #define | XV_HDMITX1_FRL_VID_CLK_OFFSET ((XV_HDMITX1_FRL_BASE)+(7*4)) |
| FRL Video Clock Register offset. More... | |
| #define | XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET ((XV_HDMITX1_FRL_BASE)+(8*4)) |
| FRL Video Packetizer FIFO Threshold Register offset. More... | |
| #define | XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(9*4)) |
| FRL Disparity Error Injector Register offset. More... | |
| #define | XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(10*4)) |
| FRL FEC Error Injector Register offset. More... | |
| #define | XV_HDMITX1_FRL_CTRL_RSTN_MASK (1<<0) |
| FRL Control Resetn mask. More... | |
| #define | XV_HDMITX1_FRL_CTRL_IE_MASK (1<<1) |
| FRL Control Interrupt Enable mask. More... | |
| #define | XV_HDMITX1_FRL_CTRL_OP_MODE_MASK (1<<2) |
| FRL Control Operation Mode mask. More... | |
| #define | XV_HDMITX1_FRL_CTRL_LN_OP_MASK (1<<3) |
| FRL Control Lane Operation mask. More... | |
| #define | XV_HDMITX1_FRL_CTRL_EXEC_MASK (1<<4) |
| FRL execute mask. More... | |
| #define | XV_HDMITX1_FRL_CTRL_TST_RC_MASK (1<<5) |
| FRL RC Compress mask. More... | |
| #define | XV_HDMITX1_FRL_ACT_MASK (1<<7) |
| FRL Control Active mask. More... | |
| #define | XV_HDMITX1_FRL_LTP0_REQ_MASK 0xF |
| FRL Control Lane 0 LTP mask. More... | |
| #define | XV_HDMITX1_FRL_LTP0_REQ_SHIFT 8 |
| FRL Control Lane 0 LTP shift. More... | |
| #define | XV_HDMITX1_FRL_LTP1_REQ_MASK 0xF |
| FRL Control Lane 1 LTP mask. More... | |
| #define | XV_HDMITX1_FRL_LTP1_REQ_SHIFT 12 |
| FRL Control Lane 1 LTP shift. More... | |
| #define | XV_HDMITX1_FRL_LTP2_REQ_MASK 0xF |
| FRL Control Lane 2 LTP mask. More... | |
| #define | XV_HDMITX1_FRL_LTP2_REQ_SHIFT 16 |
| FRL Control Lane 2 LTP shift. More... | |
| #define | XV_HDMITX1_FRL_LTP3_REQ_MASK 0xF |
| FRL Control Lane 3 LTP mask. More... | |
| #define | XV_HDMITX1_FRL_LTP3_REQ_SHIFT 20 |
| FRL Control Lane 3 LTP shift. More... | |
| #define | XV_HDMITX1_FRL_VCKE_EXT_MASK (1<<24) |
| FRL Control Lane 3 LTP mask. More... | |
| #define | XV_HDMITX1_FRL_STA_IRQ_MASK (1<<0) |
| FRL Status Interrupt mask. More... | |
| #define | XV_HDMITX1_FRL_STA_TMR_EVT_MASK (1<<1) |
| FRL Status Timer Event mask. More... | |
| #define | XV_HDMITX1_FRL_STA_TMR_ZERO_MASK (1<<2) |
| FRL Status Timer Zero mask. More... | |
| #define | XV_HDMITX1_FRL_STA_FRL_RST_MASK (1<<3) |
| FRL Status FRL Reset mask. More... | |
| #define | XV_HDMITX1_FRL_STA_TRIB_RST_MASK (1<<4) |
| FRL Status TRIB Reset mask. More... | |
| #define | XV_HDMITX1_FRL_STA_LNK_CLK_OOS_MASK (1<<5) |
| FRL Status Link Clock OOS mask. More... | |
| #define | XV_HDMITX1_FRL_STA_VID_CLK_OOS_MASK (1<<6) |
| FRL Status Video Clock OOS mask. More... | |
| #define | XV_HDMITX1_FRL_STA_GB_EP_MASK (1<<7) |
| FRL Status Gearbox EP mask. More... | |
| #define | XV_HDMITX1_FRL_STA_GB_SYNC_ERR_MASK (1<<8) |
| FRL Status Gearbox Sync Error mask. More... | |
| #define | XV_HDMITX1_FRL_LNK_CLK_MASK 0xFFFFF |
| FRL Link Clock mask. More... | |
| #define | XV_HDMITX1_FRL_VID_CLK_MASK 0xFFFFF |
| FRL Video Clock mask. More... | |
| #define | XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET ((XV_HDMITX1_FRL_BASE)+(8*4)) |
| FRL Video Packetizer FIFO Threshold Register offset. More... | |
| #define | XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(9*4)) |
| FRL Disparity Error Injector Register offset. More... | |
| #define | XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(10*4)) |
| FRL FEC Error Injector Register offset. More... | |
| #define | XV_HDMITX1_SHIFT_16 16 |
| 16 shift value More... | |
| #define | XV_HDMITX1_MASK_16 0xFFFF |
| 16 bit mask value More... | |
| #define | XV_HDMITX1_PIO_ID 0x2200 |
| TX's PIO ID. More... | |
| #define | XV_HdmiTx1_In32 Xil_In32 |
| Input Operations. More... | |
| #define | XV_HdmiTx1_Out32 Xil_Out32 |
| Output Operations. More... | |
| #define | XV_HdmiTx1_ReadReg(BaseAddress, RegOffset) XV_HdmiTx1_In32((BaseAddress) + (RegOffset)) |
| This macro reads a value from a HDMI TX register. More... | |
| #define | XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data) XV_HdmiTx1_Out32((BaseAddress) + (RegOffset), (u32)(Data)) |
| This macro writes a value to a HDMI TX register. More... | |
| #define XV_HDMITX1_3DAUD_CTRL_CH_MASK 0x07 |
3D AUD Control channels mask
Referenced by XV_HdmiTx1_SetAudioChannels().
| #define XV_HDMITX1_3DAUD_CTRL_CH_SHIFT 18 |
3D AUD Control channels mask
Referenced by XV_HdmiTx1_SetAudioChannels().
| #define XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_MASK 0xFFFF |
Analyzer hbp size mask.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_SHIFT 16 |
Analyzer hbp size shift.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_MASK 0xFFFF |
Analyzer hsync size mask.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_SHIFT 0 |
Analyzer hsync size shift.
| #define XV_HDMITX1_ANLZ_HBP_HS_OFFSET ((XV_HDMITX1_VER_BASE)+(5*4)) |
Analyzer HPB HS Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_MASK 0xFFFF |
Analyzer analyzer act size mask.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_SHIFT 0 |
Analyzer analyzer act size shift.
| #define XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_MASK 0xFFFF |
Analyzer analyzer line act mask.
PIO (Parallel Interface) peripheral register offsets The PIO is the first peripheral on the local bus
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_SHIFT 16 |
Analyzer analyzer line act shift.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_ANLZ_LN_ACT_OFFSET ((XV_HDMITX1_VER_BASE)+(6*4)) |
Analyzer LN ACT Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_AUD_ACR_CTS_MASK 0xFFFFF |
AUD ACR CTS mask.
| #define XV_HDMITX1_AUD_ACR_CTS_OFFSET ((XV_HDMITX1_AUD_BASE)+(6*4)) |
AUD Clock Regeneration N * Register offset.
Referenced by XV_HdmiTxSs1_GetAudioCtsVal().
| #define XV_HDMITX1_AUD_ACR_CTS_VLD_MASK (1<<31) |
AUD ACR CTS Valid mask.
| #define XV_HDMITX1_AUD_ACR_N_MASK 0xFFFFF |
AUD ACR N mask.
| #define XV_HDMITX1_AUD_ACR_N_OFFSET ((XV_HDMITX1_AUD_BASE)+(5*4)) |
AUD Clock Regeneration CTS * Register offset.
Referenced by XV_HdmiTx1_FRLACRStart(), XV_HdmiTx1_TMDSACRStart(), and XV_HdmiTxSs1_GetAudioNVal().
| #define XV_HDMITX1_AUD_CTRL_3DAUDFMT_EN (0x1 << XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT) |
3DAUD en
Referenced by XV_HdmiTx1_SetAudioFormat().
| #define XV_HDMITX1_AUD_CTRL_3DAUDFMT_MASK (0x3 << 16) |
3D AUD Control AUD Format mask
Referenced by XV_HdmiTx1_GetAudioFormat(), and XV_HdmiTx1_SetAudioFormat().
| #define XV_HDMITX1_AUD_CTRL_3DAUDFMT_SHIFT 16 |
3DAUD Control AUD Format Format shift
| #define XV_HDMITX1_AUD_CTRL_AUDFMT_MASK (1<<4) |
AUD Control AUD Format mask.
Referenced by XV_HdmiTx1_GetAudioFormat(), and XV_HdmiTx1_SetAudioFormat().
| #define XV_HDMITX1_AUD_CTRL_AUDFMT_SHIFT 4 |
AUD Control AUD Format shift.
Referenced by XV_HdmiTx1_GetAudioFormat().
| #define XV_HDMITX1_AUD_CTRL_CH_MASK 0x03 |
AUD Control channels mask.
Referenced by XV_HdmiTx1_SetAudioChannels().
| #define XV_HDMITX1_AUD_CTRL_CH_SHIFT 2 |
AUD Control channels mask.
Referenced by XV_HdmiTx1_SetAudioChannels().
| #define XV_HDMITX1_AUD_CTRL_CLR_OFFSET ((XV_HDMITX1_AUD_BASE)+(3*4)) |
AUD Control Register Clear * offset.
Referenced by XV_HdmiTx1_CfgInitialize(), XV_HdmiTx1_FRLACRStart(), XV_HdmiTx1_SetAudioChannels(), XV_HdmiTx1_SetAudioFormat(), and XV_HdmiTx1_TMDSACRStart().
| #define XV_HDMITX1_AUD_CTRL_IE_MASK (1<<1) |
AUD Control Interrupt Enable mask.
| #define XV_HDMITX1_AUD_CTRL_OFFSET ((XV_HDMITX1_AUD_BASE)+(1*4)) |
AUD Control Register * offset.
Referenced by XV_HdmiTx1_GetAudioFormat(), XV_HdmiTx1_SetAudioChannels(), and XV_HdmiTx1_SetAudioFormat().
| #define XV_HDMITX1_AUD_CTRL_RUN_MASK (1<<0) |
AUD Control Run mask.
Referenced by XV_HdmiTx1_AudioEnable(), XV_HdmiTx1_SetAudioChannels(), and XV_HdmiTx1_SetAudioFormat().
| #define XV_HDMITX1_AUD_CTRL_SET_OFFSET ((XV_HDMITX1_AUD_BASE)+(2*4)) |
AUD Control Register Set * offset.
Referenced by XV_HdmiTx1_AudioEnable(), XV_HdmiTx1_CfgInitialize(), XV_HdmiTx1_FRLACRStart(), XV_HdmiTx1_SetAudioChannels(), XV_HdmiTx1_SetAudioFormat(), and XV_HdmiTx1_TMDSACRStart().
| #define XV_HDMITX1_AUD_ID_OFFSET ((XV_HDMITX1_AUD_BASE)+(0*4)) |
AUD Identification * Register offset.
| #define XV_HDMITX1_AUD_STA_IRQ_MASK (1<<0) |
AUD Status Interrupt mask.
| #define XV_HDMITX1_AUD_STA_OFFSET ((XV_HDMITX1_AUD_BASE)+(4*4)) |
AUD Status Register * offset.
| #define XV_HDMITX1_AUX_CTRL_CLR_OFFSET ((XV_HDMITX1_AUX_BASE)+(3*4)) |
AUX Control Register Clear * offset.
| #define XV_HDMITX1_AUX_CTRL_DATASET_LEN_EN_MASK (1<<10) |
AUX Control Data Set Length En mask.
| #define XV_HDMITX1_AUX_CTRL_DSC_EN_MASK (1<<8) |
AUX Control DSC En mask.
| #define XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK (1 << 4) |
AUX Control Enable Dynamic HDR mask.
| #define XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK (1 << 7) |
AUX Control FAPA Location value mask.
| #define XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK (1 << 5) |
AUX Control Enable Graphic Overlay Flag mask.
| #define XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK (1 << 6) |
AUX Control Graphic Overlay Flag value mask.
| #define XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK (1<<3) |
AUX Control FSync En mask.
| #define XV_HDMITX1_AUX_CTRL_IE_MASK (1<<1) |
AUX Control Interrupt Enable mask.
| #define XV_HDMITX1_AUX_CTRL_OFFSET ((XV_HDMITX1_AUX_BASE)+(1*4)) |
AUX Control Register * offset.
| #define XV_HDMITX1_AUX_CTRL_RUN_MASK (1<<0) |
AUX Control Run mask.
Referenced by XV_HdmiTx1_AuxEnable().
| #define XV_HDMITX1_AUX_CTRL_SET_OFFSET ((XV_HDMITX1_AUX_BASE)+(2*4)) |
AUX Control Register Set * offset.
Referenced by XV_HdmiTx1_AuxEnable().
| #define XV_HDMITX1_AUX_CTRL_SYNC_EN_MASK (1<<9) |
AUX Control SYNC En mask.
| #define XV_HDMITX1_AUX_CTRL_VRR_EN_MASK (1<<2) |
AUX Control VRR En mask.
| #define XV_HDMITX1_AUX_DAT_OFFSET ((XV_HDMITX1_AUX_BASE)+(5*4)) |
AUX Data Register * offset.
Referenced by XV_HdmiTx1_AuxSend().
| #define XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET (XV_HDMITX1_AUX_BASE + (10 * 4)) |
AUX Dynamic HDR Address LSB offset.
| #define XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET (XV_HDMITX1_AUX_BASE + (11 * 4)) |
AUX Dynamic HDR Address MSB offset.
| #define XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET (XV_HDMITX1_AUX_BASE + (9 * 4)) |
AUX Dynamic HDR Packet offset.
| #define XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK (1 << 9) |
AUX Status Dynamic HDR read response.
| #define XV_HDMITX1_AUX_FSYNC_OFFSET ((XV_HDMITX1_AUX_BASE)+(7*4)) |
AUX FSYNC Register offset.
| #define XV_HDMITX1_AUX_FSYNC_PRO_OF ((XV_HDMITX1_AUX_BASE)+(8*4)) |
AUX FYNC PRO Register offset.
| #define XV_HDMITX1_AUX_ID_OFFSET ((XV_HDMITX1_AUX_BASE)+(0*4)) |
AUX Identification * Register offset.
| #define XV_HDMITX1_AUX_STA_DSC_PKT_WRRDY_MASK (1 << 10) |
AUX Status DSC Packet Write Ready.
| #define XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK (1 << 8) |
AUX Status Dynamic HDR MTW started.
| #define XV_HDMITX1_AUX_STA_FIFO_EMT_MASK (1<<1) |
AUX Status FIFO Empty mask.
| #define XV_HDMITX1_AUX_STA_FIFO_FUL_MASK (1<<2) |
AUX Status FIFO Full mask.
Referenced by XV_HdmiTx1_AuxSend().
| #define XV_HDMITX1_AUX_STA_FREE_PKTS_MASK 0x0F |
AUX Status Free Packets mask.
| #define XV_HDMITX1_AUX_STA_FREE_PKTS_SHIFT 15 |
AUX Status Free Packets shift.
| #define XV_HDMITX1_AUX_STA_IRQ_MASK (1<<0) |
AUX Status Interrupt mask.
Referenced by XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_AUX_STA_OFFSET ((XV_HDMITX1_AUX_BASE)+(4*4)) |
AUX Status Register * offset.
Referenced by XV_HdmiTx1_AuxSend(), and XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_AUX_STA_PKT_RDY_MASK (1<<3) |
AUX Status FIFO Ready mask.
Referenced by XV_HdmiTx1_AuxSend().
| #define XV_HDMITX1_AUX_VTEM_OFFSET ((XV_HDMITX1_AUX_BASE)+(6*4)) |
AUX VTEM Register offset.
| #define XV_HDMITX1_BRDG_FIFO_LVL_MAX_MASK 0xFFFF |
FRL Control Lane 0 LTP mask.
| #define XV_HDMITX1_BRDG_FIFO_LVL_MAX_SHIFT 16 |
FRL Control Lane 0 LTP shift.
| #define XV_HDMITX1_BRDG_FIFO_LVL_MIN_MASK 0xFFFF |
FRL Control Lane 0 LTP mask.
| #define XV_HDMITX1_BRDG_FIFO_LVL_MIN_SHIFT 0 |
FRL Control Lane 0 LTP shift.
| #define XV_HDMITX1_BRDG_FIFO_LVL_OFFSET ((XV_HDMITX1_VER_BASE)+(2*4)) |
Bridge FIFO Level Register offset.
| #define XV_HDMITX1_CONNECT_CONF_OFFSET ((XV_HDMITX1_PIO_BASE)+(15*4)) |
| #define XV_HDMITX1_DBG_STS_OFFSET ((XV_HDMITX1_VER_BASE)+(4*4)) |
Debug Status Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_DDC_CFG_1_FRL_RATE_MASK 0xF |
VER (Version Interface) peripheral register offsets.
The VER is the first peripheral on the local bus
| #define XV_HDMITX1_DDC_CMD_OFFSET ((XV_HDMITX1_DDC_BASE)+(5*4)) |
DDC Command Register * offset.
Referenced by XV_HdmiTx1_DdcWriteCommand().
| #define XV_HDMITX1_DDC_CMD_RD_TOKEN (0x102) |
Read token.
Referenced by XV_HdmiTx1_DdcRead().
| #define XV_HDMITX1_DDC_CMD_STP_TOKEN (0x101) |
Stop token.
Referenced by XV_HdmiTx1_DdcRead(), and XV_HdmiTx1_DdcWrite().
| #define XV_HDMITX1_DDC_CMD_STR_TOKEN (0x100) |
Start token.
Referenced by XV_HdmiTx1_DdcRead(), and XV_HdmiTx1_DdcWrite().
| #define XV_HDMITX1_DDC_CMD_WR_TOKEN (0x103) |
Write token.
Referenced by XV_HdmiTx1_DdcRead(), and XV_HdmiTx1_DdcWrite().
| #define XV_HDMITX1_DDC_CTRL_CLK_DIV_MASK 0xFFFF |
DDC Control Clock Divider mask.
Referenced by XV_HdmiTx1_DdcInit().
| #define XV_HDMITX1_DDC_CTRL_CLR_OFFSET ((XV_HDMITX1_DDC_BASE)+(3*4)) |
DDC Control Register Clear * offset.
| #define XV_HDMITX1_DDC_CTRL_IE_MASK (1<<1) |
DDC Control Interrupt Enable mask.
| #define XV_HDMITX1_DDC_CTRL_OFFSET ((XV_HDMITX1_DDC_BASE)+(1*4)) |
DDC Control Register * offset.
Referenced by XV_HdmiTx1_DdcInit(), XV_HdmiTx1_DdcReadData(), XV_HdmiTx1_DdcWaitForDone(), and XV_HdmiTx1_DdcWriteCommand().
| #define XV_HDMITX1_DDC_CTRL_RUN_MASK (1<<0) |
DDC Control Run mask.
Referenced by XV_HdmiTx1_DdcReadData(), XV_HdmiTx1_DdcWaitForDone(), and XV_HdmiTx1_DdcWriteCommand().
| #define XV_HDMITX1_DDC_CTRL_SET_OFFSET ((XV_HDMITX1_DDC_BASE)+(2*4)) |
DDC Control Register Set * offset.
| #define XV_HDMITX1_DDC_CTRL_TO_STOP_MASK (1<<2) |
DDC Control TO Stop mask.
| #define XV_HDMITX1_DDC_DAT_OFFSET ((XV_HDMITX1_DDC_BASE)+(6*4)) |
DDC Data Register * offset.
Referenced by XV_HdmiTx1_DdcReadData().
| #define XV_HDMITX1_DDC_ID_OFFSET ((XV_HDMITX1_DDC_BASE)+(0*4)) |
DDC Identification * Register offset.
| #define XV_HDMITX1_DDC_SINK_VER_REG 0x01 |
< DDC Register Address
| #define XV_HDMITX1_DDC_STA_ACK_MASK (1<<5) |
DDC Status ACK mask.
Referenced by XV_HdmiTx1_DdcGetAck().
| #define XV_HDMITX1_DDC_STA_BUSY_MASK (1<<2) |
DDC Status Busy mask.
| #define XV_HDMITX1_DDC_STA_CMD_FULL (1<<8) |
Command fifo full.
Referenced by XV_HdmiTx1_DdcWriteCommand().
| #define XV_HDMITX1_DDC_STA_CMD_WRDS_MASK 0xFF |
Command fifo words mask.
| #define XV_HDMITX1_DDC_STA_CMD_WRDS_SHIFT 16 |
Command fifo words shift.
| #define XV_HDMITX1_DDC_STA_DAT_EMPTY (1<<9) |
Data fifo empty.
Referenced by XV_HdmiTx1_DdcReadData().
| #define XV_HDMITX1_DDC_STA_DAT_WRDS_MASK 0xFF |
Data fifo words mask.
| #define XV_HDMITX1_DDC_STA_DAT_WRDS_SHIFT 24 |
Data fifo words shift.
| #define XV_HDMITX1_DDC_STA_DONE_MASK (1<<3) |
DDC Status Busy mask.
Referenced by XV_HdmiTx1_DdcWaitForDone().
| #define XV_HDMITX1_DDC_STA_EVT_MASK (1<<1) |
DDC Status Event mask.
| #define XV_HDMITX1_DDC_STA_IRQ_MASK (1<<0) |
DDC Status IRQ mask.
Referenced by XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_DDC_STA_OFFSET ((XV_HDMITX1_DDC_BASE)+(4*4)) |
DDC Status Register * offset.
Referenced by XV_HdmiTx1_DdcGetAck(), XV_HdmiTx1_DdcReadData(), XV_HdmiTx1_DdcWaitForDone(), XV_HdmiTx1_DdcWriteCommand(), and XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_DDC_STA_SCL_MASK (1<<6) |
DDC State of SCL Input mask.
| #define XV_HDMITX1_DDC_STA_SDA_MASK (1<<7) |
DDC State of SDA Input mask.
| #define XV_HDMITX1_DDC_STA_TIMEOUT_MASK (1<<4) |
DDC Status Timeout mask.
Referenced by XV_HdmiTx1_DdcWaitForDone().
| #define XV_HDMITX1_FRL_ACT_MASK (1<<7) |
FRL Control Active mask.
Referenced by XV_HdmiTx1_SetFrlActive().
| #define XV_HDMITX1_FRL_CTRL_CLR_OFFSET ((XV_HDMITX1_FRL_BASE)+(3*4)) |
FRL Control Register Clear offset.
Referenced by XV_HdmiTx1_FrlExtVidCkeSource(), XV_HdmiTx1_FrlModeEn(), XV_HdmiTx1_FrlReset(), XV_HdmiTx1_SetFrlActive(), and XV_HdmiTx1_SetFrlLanes().
| #define XV_HDMITX1_FRL_CTRL_EXEC_MASK (1<<4) |
FRL execute mask.
Referenced by XV_HdmiTx1_FrlExecute().
| #define XV_HDMITX1_FRL_CTRL_IE_MASK (1<<1) |
FRL Control Interrupt Enable mask.
| #define XV_HDMITX1_FRL_CTRL_LN_OP_MASK (1<<3) |
FRL Control Lane Operation mask.
Referenced by XV_HdmiTx1_DebugInfo(), and XV_HdmiTx1_SetFrlLanes().
| #define XV_HDMITX1_FRL_CTRL_OFFSET ((XV_HDMITX1_FRL_BASE)+(1*4)) |
FRL Control Register offset.
Referenced by XV_HdmiTx1_DebugInfo(), and XV_HdmiTx1_SetFrlLtp().
| #define XV_HDMITX1_FRL_CTRL_OP_MODE_MASK (1<<2) |
FRL Control Operation Mode mask.
Referenced by XV_HdmiTx1_DebugInfo(), and XV_HdmiTx1_FrlModeEn().
| #define XV_HDMITX1_FRL_CTRL_RSTN_MASK (1<<0) |
FRL Control Resetn mask.
Referenced by XV_HdmiTx1_FrlReset().
| #define XV_HDMITX1_FRL_CTRL_SET_OFFSET ((XV_HDMITX1_FRL_BASE)+(2*4)) |
FRL Control Register Set offset.
Referenced by XV_HdmiTx1_FrlExecute(), XV_HdmiTx1_FrlExtVidCkeSource(), XV_HdmiTx1_FrlModeEn(), XV_HdmiTx1_FrlReset(), XV_HdmiTx1_SetFrlActive(), and XV_HdmiTx1_SetFrlLanes().
| #define XV_HDMITX1_FRL_CTRL_TST_RC_MASK (1<<5) |
FRL RC Compress mask.
| #define XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(9*4)) |
FRL Disparity Error Injector Register offset.
| #define XV_HDMITX1_FRL_DISP_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(9*4)) |
FRL Disparity Error Injector Register offset.
| #define XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(10*4)) |
FRL FEC Error Injector Register offset.
Referenced by XV_HdmiTx1_RegisterDebug().
| #define XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET ((XV_HDMITX1_FRL_BASE)+(10*4)) |
FRL FEC Error Injector Register offset.
| #define XV_HDMITX1_FRL_ID_OFFSET ((XV_HDMITX1_FRL_BASE)+(0*4)) |
FRL Identification Register offset.
| #define XV_HDMITX1_FRL_LNK_CLK_MASK 0xFFFFF |
FRL Link Clock mask.
| #define XV_HDMITX1_FRL_LNK_CLK_OFFSET ((XV_HDMITX1_FRL_BASE)+(6*4)) |
FRL Link Clock Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_FRL_LTP0_REQ_MASK 0xF |
FRL Control Lane 0 LTP mask.
Referenced by XV_HdmiTx1_SetFrlLtp().
| #define XV_HDMITX1_FRL_LTP0_REQ_SHIFT 8 |
FRL Control Lane 0 LTP shift.
Referenced by XV_HdmiTx1_SetFrlLtp().
| #define XV_HDMITX1_FRL_LTP1_REQ_MASK 0xF |
FRL Control Lane 1 LTP mask.
| #define XV_HDMITX1_FRL_LTP1_REQ_SHIFT 12 |
FRL Control Lane 1 LTP shift.
Referenced by XV_HdmiTx1_SetFrlLtp().
| #define XV_HDMITX1_FRL_LTP2_REQ_MASK 0xF |
FRL Control Lane 2 LTP mask.
| #define XV_HDMITX1_FRL_LTP2_REQ_SHIFT 16 |
FRL Control Lane 2 LTP shift.
Referenced by XV_HdmiTx1_SetFrlLtp().
| #define XV_HDMITX1_FRL_LTP3_REQ_MASK 0xF |
FRL Control Lane 3 LTP mask.
| #define XV_HDMITX1_FRL_LTP3_REQ_SHIFT 20 |
FRL Control Lane 3 LTP shift.
Referenced by XV_HdmiTx1_SetFrlLtp().
| #define XV_HDMITX1_FRL_STA_FRL_RST_MASK (1<<3) |
FRL Status FRL Reset mask.
| #define XV_HDMITX1_FRL_STA_GB_EP_MASK (1<<7) |
FRL Status Gearbox EP mask.
| #define XV_HDMITX1_FRL_STA_GB_SYNC_ERR_MASK (1<<8) |
FRL Status Gearbox Sync Error mask.
| #define XV_HDMITX1_FRL_STA_IRQ_MASK (1<<0) |
FRL Status Interrupt mask.
Referenced by XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_FRL_STA_LNK_CLK_OOS_MASK (1<<5) |
FRL Status Link Clock OOS mask.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_FRL_STA_OFFSET ((XV_HDMITX1_FRL_BASE)+(4*4)) |
FRL Status Register offset.
Referenced by XV_HdmiTx1_DebugInfo(), and XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_FRL_STA_TMR_EVT_MASK (1<<1) |
FRL Status Timer Event mask.
| #define XV_HDMITX1_FRL_STA_TMR_ZERO_MASK (1<<2) |
FRL Status Timer Zero mask.
| #define XV_HDMITX1_FRL_STA_TRIB_RST_MASK (1<<4) |
FRL Status TRIB Reset mask.
| #define XV_HDMITX1_FRL_STA_VID_CLK_OOS_MASK (1<<6) |
FRL Status Video Clock OOS mask.
| #define XV_HDMITX1_FRL_TMR_OFFSET ((XV_HDMITX1_FRL_BASE)+(5*4)) |
FRL Timer Register offset.
Referenced by XV_HdmiTx1_GetFrlTimer(), XV_HdmiTx1_SetFrl10MicroSecondsTimer(), XV_HdmiTx1_SetFrlTimer(), and XV_HdmiTx1_SetFrlTimerClockCycles().
| #define XV_HDMITX1_FRL_VCKE_EXT_MASK (1<<24) |
FRL Control Lane 3 LTP mask.
Referenced by XV_HdmiTx1_DebugInfo(), and XV_HdmiTx1_FrlExtVidCkeSource().
| #define XV_HDMITX1_FRL_VID_CLK_MASK 0xFFFFF |
FRL Video Clock mask.
| #define XV_HDMITX1_FRL_VID_CLK_OFFSET ((XV_HDMITX1_FRL_BASE)+(7*4)) |
FRL Video Clock Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET ((XV_HDMITX1_FRL_BASE)+(8*4)) |
FRL Video Packetizer FIFO Threshold Register offset.
| #define XV_HDMITX1_FRL_VP_FIFO_THRD_OFFSET ((XV_HDMITX1_FRL_BASE)+(8*4)) |
FRL Video Packetizer FIFO Threshold Register offset.
| #define XV_HDMITX1_HPD_TIMEGRID_OFFSET ((XV_HDMITX1_PIO_BASE)+(13*4)) |
| #define XV_HDMITX1_HW_H_ |
Prevent circular inclusions by using protection macros.
| #define XV_HdmiTx1_In32 Xil_In32 |
Input Operations.
| #define XV_HDMITX1_MASK_16 0xFFFF |
16 bit mask value
Referenced by XV_HdmiTx1_CfgInitialize(), and XV_HdmiTx1_SelfTest().
| #define XV_HDMITX1_MASK_BLUE_OFFSET ((XV_HDMITX1_MASK_BASE)+(7*4)) |
MASK Blue Component Register offset.
| #define XV_HDMITX1_MASK_CTRL_CLR_OFFSET ((XV_HDMITX1_MASK_BASE)+(3*4)) |
MASK Control Register Clear offset.
| #define XV_HDMITX1_MASK_CTRL_NOISE_MASK (1<<2) |
MASK Control Noise.
| #define XV_HDMITX1_MASK_CTRL_OFFSET ((XV_HDMITX1_MASK_BASE)+(1*4)) |
MASK Control Register offset.
| #define XV_HDMITX1_MASK_CTRL_RUN_MASK (1<<0) |
MASK Control Run mask.
| #define XV_HDMITX1_MASK_CTRL_SET_OFFSET ((XV_HDMITX1_MASK_BASE)+(2*4)) |
MASK Control Register Set offset.
| #define XV_HDMITX1_MASK_GREEN_OFFSET ((XV_HDMITX1_MASK_BASE)+(6*4)) |
MASK Green Component Register offset.
| #define XV_HDMITX1_MASK_ID_OFFSET ((XV_HDMITX1_MASK_BASE)+(0*4)) |
MASK Identification Register offset.
| #define XV_HDMITX1_MASK_RED_OFFSET ((XV_HDMITX1_MASK_BASE)+(5*4)) |
MASK Red Component Register offset.
| #define XV_HDMITX1_MASK_STA_OFFSET ((XV_HDMITX1_MASK_BASE)+(4*4)) |
MASK Status Register offset.
| #define XV_HdmiTx1_Out32 Xil_Out32 |
Output Operations.
| #define XV_HDMITX1_PIO_CTRL_CLR_OFFSET ((XV_HDMITX1_PIO_BASE)+(3*4)) |
PIO Control Register Clear * offset.
| #define XV_HDMITX1_PIO_CTRL_IE_MASK (1<<1) |
PIO Control Interrupt Enable mask.
| #define XV_HDMITX1_PIO_CTRL_OFFSET ((XV_HDMITX1_PIO_BASE)+(1*4)) |
PIO Control Register * offset.
| #define XV_HDMITX1_PIO_CTRL_RUN_MASK (1<<0) |
PIO Control Run mask.
| #define XV_HDMITX1_PIO_CTRL_SET_OFFSET ((XV_HDMITX1_PIO_BASE)+(2*4)) |
PIO Control Register Set * offset.
| #define XV_HDMITX1_PIO_ID 0x2200 |
TX's PIO ID.
Referenced by XV_HdmiTx1_CfgInitialize(), and XV_HdmiTx1_SelfTest().
| #define XV_HDMITX1_PIO_ID_OFFSET ((XV_HDMITX1_PIO_BASE)+(0*4)) |
PIO Identification * Register offset.
Referenced by XV_HdmiTx1_CfgInitialize(), and XV_HdmiTx1_SelfTest().
| #define XV_HDMITX1_PIO_IN_BRDG_LOCKED_MASK (1<<9) |
PIO In Bridge Locked mask.
Referenced by XV_HdmiTx1_CfgInitialize(), and XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_PIO_IN_BRDG_OVERFLOW_MASK (1<<10) |
PIO In Bridge Overflow mask.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_BRDG_UNDERFLOW_MASK (1<<11) |
PIO In Bridge Underflow mask.
DDC (Display Data Channel) peripheral register offsets The DDC is the second peripheral on the local bus
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_EVT_FE_OFFSET ((XV_HDMITX1_PIO_BASE)+(12*4)) |
PIO In Event Falling Edge Register offset.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_EVT_OFFSET ((XV_HDMITX1_PIO_BASE)+(10*4)) |
PIO In Event Register * offset.
| #define XV_HDMITX1_PIO_IN_EVT_RE_OFFSET ((XV_HDMITX1_PIO_BASE)+(11*4)) |
PIO In Event Rising Edge Register offset.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_HPD_MASK (1<<2) |
PIO In HPD mask.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_HPD_TOGGLE_MASK (1<<8) |
PIO In HPD toggle mask.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_LNK_RDY_MASK (1<<0) |
PIO In link ready mask.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_IN_OFFSET ((XV_HDMITX1_PIO_BASE)+(9*4)) |
PIO In Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_PIO_IN_PPP_MASK 0x07 |
PIO In Pixel packing phase mask.
| #define XV_HDMITX1_PIO_IN_PPP_SHIFT 5 |
PIO In Pixel packing phase shift.
| #define XV_HDMITX1_PIO_IN_VID_RDY_MASK (1<<1) |
PIO In video ready mask.
| #define XV_HDMITX1_PIO_IN_VS_MASK (1<<3) |
PIO In Vsync mask.
Referenced by XV_HdmiTx1_CfgInitialize().
| #define XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK (1<<30) |
PIO Out Bridge_Pixel repeat mask.
| #define XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK (1<<29) |
PIO Out Bridge_YUV420 mask.
| #define XV_HDMITX1_PIO_OUT_CLR_OFFSET ((XV_HDMITX1_PIO_BASE)+(7*4)) |
PIO Out Register Clear * offset.
Referenced by XV_HdmiTx1_ClearGcpAvmuteBit(), XV_HdmiTx1_ClearGcpClearAvmuteBit(), XV_HdmiTx1_EXT_SYSRST(), XV_HdmiTx1_EXT_VRST(), XV_HdmiTx1_INT_LRST(), and XV_HdmiTx1_INT_VRST().
| #define XV_HDMITX1_PIO_OUT_COLOR_DEPTH_MASK 0x30 |
PIO Out Color Depth mask.
Referenced by XV_HdmiTx1_SetColorDepth().
| #define XV_HDMITX1_PIO_OUT_COLOR_DEPTH_SHIFT 4 |
PIO Out Color Depth shift.
Referenced by XV_HdmiTx1_SetColorDepth().
| #define XV_HDMITX1_PIO_OUT_COLOR_SPACE_MASK 0xC00 |
PIO Out Color Space mask.
Referenced by XV_HdmiTx1_SetColorFormat().
| #define XV_HDMITX1_PIO_OUT_COLOR_SPACE_SHIFT 10 |
PIO Out Color Space shift.
Referenced by XV_HdmiTx1_SetColorFormat().
| #define XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK (1 << 23) |
PIO Out Dynamic HDR Data Mover Enable.
| #define XV_HDMITX1_PIO_OUT_EXT_SYSRST_MASK (1<<22) |
PIO Out EXT_SYSRST mask.
Referenced by XV_HdmiTx1_EXT_SYSRST().
| #define XV_HDMITX1_PIO_OUT_EXT_VRST_MASK (1<<21) |
PIO Out EXT_VRST mask.
Referenced by XV_HdmiTx1_EXT_VRST().
| #define XV_HDMITX1_PIO_OUT_GCP_AVMUTE_MASK (1<<31) |
PIO Out GCP_AVMUTE mask.
Referenced by XV_HdmiTx1_ClearGcpAvmuteBit(), and XV_HdmiTx1_SetGcpAvmuteBit().
| #define XV_HDMITX1_PIO_OUT_GCP_CLEARAVMUTE_MASK (1<<28) |
PIO Out GCP_CLEARAVMUTE mask.
Referenced by XV_HdmiTx1_ClearGcpClearAvmuteBit(), and XV_HdmiTx1_SetGcpClearAvmuteBit().
| #define XV_HDMITX1_PIO_OUT_INT_LRST_MASK (1<<20) |
PIO Out INT_LRST mask.
Referenced by XV_HdmiTx1_INT_LRST().
| #define XV_HDMITX1_PIO_OUT_INT_VRST_MASK (1<<0) |
PIO Out INT_VRST mask.
Referenced by XV_HdmiTx1_INT_VRST().
| #define XV_HDMITX1_PIO_OUT_MODE_MASK (1<<3) |
PIO Out Mode mask.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_PIO_OUT_MSK_OFFSET ((XV_HDMITX1_PIO_BASE)+(8*4)) |
PIO Out Mask Register * offset.
Referenced by XV_HdmiTx1_SetColorDepth(), XV_HdmiTx1_SetColorFormat(), XV_HdmiTx1_SetPixelRate(), and XV_HdmiTx1_SetSampleRate().
| #define XV_HDMITX1_PIO_OUT_OFFSET ((XV_HDMITX1_PIO_BASE)+(5*4)) |
PIO Out Register offset.
Referenced by XV_HdmiTx1_DebugInfo(), XV_HdmiTx1_SetColorDepth(), XV_HdmiTx1_SetColorFormat(), XV_HdmiTx1_SetPixelRate(), and XV_HdmiTx1_SetSampleRate().
| #define XV_HDMITX1_PIO_OUT_PIXEL_RATE_MASK 0xC0 |
PIO Out Pixel Rate mask.
Referenced by XV_HdmiTx1_SetPixelRate().
| #define XV_HDMITX1_PIO_OUT_PIXEL_RATE_SHIFT 6 |
PIO Out Pixel Rate shift.
Referenced by XV_HdmiTx1_SetPixelRate().
| #define XV_HDMITX1_PIO_OUT_RST_MASK (1<<0) |
PIO Out Reset mask.
| #define XV_HDMITX1_PIO_OUT_SAMPLE_RATE_MASK 0x300 |
PIO Out Sample Rate mask.
Referenced by XV_HdmiTx1_SetSampleRate().
| #define XV_HDMITX1_PIO_OUT_SAMPLE_RATE_SHIFT 8 |
PIO Out Sample Rate shift.
Referenced by XV_HdmiTx1_SetSampleRate().
| #define XV_HDMITX1_PIO_OUT_SCRM_MASK (1<<12) |
PIO Out Scrambler mask.
| #define XV_HDMITX1_PIO_OUT_SET_OFFSET ((XV_HDMITX1_PIO_BASE)+(6*4)) |
PIO Out Register Set * offset.
Referenced by XV_HdmiTx1_EXT_SYSRST(), XV_HdmiTx1_EXT_VRST(), XV_HdmiTx1_INT_LRST(), XV_HdmiTx1_INT_VRST(), XV_HdmiTx1_SetGcpAvmuteBit(), and XV_HdmiTx1_SetGcpClearAvmuteBit().
| #define XV_HDMITX1_PIO_STA_EVT_MASK (1<<1) |
PIO Status Event mask.
| #define XV_HDMITX1_PIO_STA_IRQ_MASK (1<<0) |
PIO Status Interrupt mask.
Referenced by XV_HdmiTx1_IntrHandler().
| #define XV_HDMITX1_PIO_STA_OFFSET ((XV_HDMITX1_PIO_BASE)+(4*4)) |
PIO Status Register * offset.
Referenced by XV_HdmiTx1_IntrHandler().
| #define XV_HdmiTx1_ReadReg | ( | BaseAddress, | |
| RegOffset | |||
| ) | XV_HdmiTx1_In32((BaseAddress) + (RegOffset)) |
This macro reads a value from a HDMI TX register.
A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.
| BaseAddress | is the base address of the HDMI TX core instance. |
| RegOffset | is the register offset of the register (defined at the top of this file). |
Referenced by XV_HdmiTx1_AuxSend(), XV_HdmiTx1_CfgInitialize(), XV_HdmiTx1_DdcGetAck(), XV_HdmiTx1_DdcReadData(), XV_HdmiTx1_DdcWaitForDone(), XV_HdmiTx1_DdcWriteCommand(), XV_HdmiTx1_DebugInfo(), XV_HdmiTx1_GetAudioFormat(), XV_HdmiTx1_GetFrlTimer(), XV_HdmiTx1_IntrHandler(), XV_HdmiTx1_RegisterDebug(), XV_HdmiTx1_SelfTest(), XV_HdmiTx1_SetAudioChannels(), XV_HdmiTx1_SetAudioFormat(), XV_HdmiTx1_SetFrlLtp(), XV_HdmiTxSs1_GetAudioCtsVal(), and XV_HdmiTxSs1_GetAudioNVal().
| #define XV_HDMITX1_SHIFT_16 16 |
16 shift value
Referenced by XV_HdmiTx1_CfgInitialize(), and XV_HdmiTx1_SelfTest().
| #define XV_HDMITX1_TOGGLE_CONF_OFFSET ((XV_HDMITX1_PIO_BASE)+(14*4)) |
| #define XV_HDMITX1_VCKE_SYS_CNT_OFFSET ((XV_HDMITX1_VER_BASE)+(3*4)) |
VCKE System Count Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_VER_ID_OFFSET ((XV_HDMITX1_VER_BASE)+(0*4)) |
VER Identification * Register offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HDMITX1_VER_VERSION_OFFSET ((XV_HDMITX1_VER_BASE)+(1*4)) |
VER Version Register * offset.
Referenced by XV_HdmiTx1_DebugInfo().
| #define XV_HdmiTx1_WriteReg | ( | BaseAddress, | |
| RegOffset, | |||
| Data | |||
| ) | XV_HdmiTx1_Out32((BaseAddress) + (RegOffset), (u32)(Data)) |
This macro writes a value to a HDMI TX register.
A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.
| BaseAddress | is the base address of the HDMI TX core instance. |
| RegOffset | is the register offset of the register (defined at the top of this file) to be written. |
| Data | is the 32-bit value to write into the register. |
Referenced by XV_HdmiTx1_AudioEnable(), XV_HdmiTx1_Aux_Dsc_Send_Data(), XV_HdmiTx1_Aux_Dsc_Send_Header(), XV_HdmiTx1_AuxEnable(), XV_HdmiTx1_AuxSend(), XV_HdmiTx1_CfgInitialize(), XV_HdmiTx1_ClearGcpAvmuteBit(), XV_HdmiTx1_ClearGcpClearAvmuteBit(), XV_HdmiTx1_DdcInit(), XV_HdmiTx1_DdcWaitForDone(), XV_HdmiTx1_DdcWriteCommand(), XV_HdmiTx1_EXT_SYSRST(), XV_HdmiTx1_EXT_VRST(), XV_HdmiTx1_FRLACRStart(), XV_HdmiTx1_FrlExecute(), XV_HdmiTx1_FrlExtVidCkeSource(), XV_HdmiTx1_FrlModeEn(), XV_HdmiTx1_FrlReset(), XV_HdmiTx1_INT_LRST(), XV_HdmiTx1_INT_VRST(), XV_HdmiTx1_SetAudioChannels(), XV_HdmiTx1_SetAudioFormat(), XV_HdmiTx1_SetColorDepth(), XV_HdmiTx1_SetColorFormat(), XV_HdmiTx1_SetFrl10MicroSecondsTimer(), XV_HdmiTx1_SetFrlActive(), XV_HdmiTx1_SetFrlLanes(), XV_HdmiTx1_SetFrlLtp(), XV_HdmiTx1_SetFrlTimer(), XV_HdmiTx1_SetFrlTimerClockCycles(), XV_HdmiTx1_SetGcpAvmuteBit(), XV_HdmiTx1_SetGcpClearAvmuteBit(), XV_HdmiTx1_SetPixelRate(), XV_HdmiTx1_SetSampleRate(), and XV_HdmiTx1_TMDSACRStart().