v_hdmirx1
Vitis Drivers API Documentation
Functions | Variables
xv_hdmirx1_frl.c File Reference

Overview

This is the main file for Xilinx HDMI RX core for FRL.

Please see xv_hdmirx1_frl.h for more details of the driver.

MODIFICATION HISTORY:
Ver   Who    Date     Changes






1.00  EB     25/06/18 Initial release.

Functions

void XV_HdmiRx1_FrlModeEnable (XV_HdmiRx1 *InstancePtr, u8 LtpThreshold, XV_HdmiRx1_FrlLtp DefaultLtp, u8 FfeSuppFlag)
 This function enables the FRL mode. More...
 
int XV_HdmiRx1_ExecFrlState (XV_HdmiRx1 *InstancePtr)
 This function executes the different of states of FRL. More...
 
u32 XV_HdmiRx1_GetPatternsMatchStatus (XV_HdmiRx1 *InstancePtr)
 This function returns the status of the patterns matched lanes. More...
 
void XV_HdmiRx1_PhyResetPoll (XV_HdmiRx1 *InstancePtr)
 This function polls the pattern matching status and decide if the Phy needs to be reset or not. More...
 
void XV_HdmiRx1_SetFrlLtpDetection (XV_HdmiRx1 *InstancePtr, u8 Lane, XV_HdmiRx1_FrlLtpType Ltp)
 This function sets the link training pattern to be detected for the selected lane. More...
 
u32 XV_HdmiRx1_GetFrlLtpDetection (XV_HdmiRx1 *InstancePtr, u8 Lane)
 This function returns the link training pattern to be detected for the selected lane. More...
 
u32 XV_HdmiRx1_GetFrlTotalPixRatio (XV_HdmiRx1 *InstancePtr)
 This function provides FRL Ratio (Total Pixel) More...
 
u32 XV_HdmiRx1_GetFrlActivePixRatio (XV_HdmiRx1 *InstancePtr)
 This function provides FRL Ratio (Active Pixel) More...
 
void XV_HdmiRx1_ResetFrlLtpDetection (XV_HdmiRx1 *InstancePtr)
 This function reset the link training pattern for the specified lane. More...
 
void XV_HdmiRx1_FrlLtpDetectionEnable (XV_HdmiRx1 *InstancePtr)
 This function enables the LTP detection module. More...
 
void XV_HdmiRx1_FrlLtpDetectionDisable (XV_HdmiRx1 *InstancePtr)
 This function disables the LTP detection module. More...
 
void XV_HdmiRx1_SetFrlLtpThreshold (XV_HdmiRx1 *InstancePtr, u8 Threshold)
 This function sets the number of times the full link training patterns need to be matched before it is considered as a lock. More...
 
int XV_HdmiRx1_ConfigFrlLtpDetection (XV_HdmiRx1 *InstancePtr)
 This function configures the link training pattern to be detected. More...
 
int XV_HdmiRx1_RetrieveFrlRateLanes (XV_HdmiRx1 *InstancePtr)
 This function updates the software's FRL Rate and FRL Lanes by reading and decoding the information from the RX core. More...
 
void XV_HdmiRx1_FrlLinkRetrain (XV_HdmiRx1 *InstancePtr, u8 LtpThreshold, XV_HdmiRx1_FrlLtp DefaultLtp)
 This function initiates FRL rate dropping procedure. More...
 
u32 XV_HdmiRx1_FrlDdcReadField (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field)
 This function reads the specified FRL SCDC Field. More...
 
int XV_HdmiRx1_FrlDdcWriteField (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)
 This function writes the specified FRL SCDC Field. More...
 
void XV_HdmiRx1_SetFrlRateWrEvent_En (XV_HdmiRx1 *InstancePtr)
 This function sets the FRL rate write enable Event. More...
 
void XV_HdmiRx1_FrlReset (XV_HdmiRx1 *InstancePtr, u8 Reset)
 This function resets the FRL peripheral. More...
 
void XV_HdmiRx1_SetFrl10MicroSecondsTimer (XV_HdmiRx1 *InstancePtr)
 This function sets the timer of RX Core's FRL peripheral for 10 Microseconds. More...
 

Variables

const u16 FrlTimeoutLts3 [4]
 This table contains the timeout period of LTS3 for different FFE Levels in Milliseconds. More...
 
const XV_HdmiRx1_FrlScdcField FrlScdcField [XV_HDMIRX1_SCDCFIELD_SIZE]
 This table contains the attributes for SCDC fields Each entry consists of: 1) Register Offset 2) Bits Mask 3) Bits Shift. More...
 

Function Documentation

int XV_HdmiRx1_ConfigFrlLtpDetection ( XV_HdmiRx1 *  InstancePtr)

This function configures the link training pattern to be detected.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Status
  • XST_FAILURE
    • Source has not cleared FLT_update so sink should not update FLT_req and FLT_update as to ensure proper data handshake
    • XST_SUCCESS
    • Source has cleared FLT_update and sink has updated LTP_req and set FLT_update to 1
    • XST_NO_DATA
    • Source has cleared FLT_update but no update from sink is required
Note
None.

References XV_HdmiRx1::Config, XV_HdmiRx1_Frl::CurFrlRate, XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Frl::Ltp, XV_HdmiRx1::Stream, XV_HdmiRx1_Frl::TrainingState, XV_HdmiRx1_GetFrlLtpDetection(), XV_HdmiRx1_GetTmr1Value, XV_HdmiRx1_ResetFrlLtpDetection(), and XV_HdmiRx1_SetFrlLtpDetection().

int XV_HdmiRx1_ExecFrlState ( XV_HdmiRx1 *  InstancePtr)

This function executes the different of states of FRL.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1::Stream, and XV_HdmiRx1_Frl::TrainingState.

Referenced by XV_HdmiRx1_FrlLinkRetrain(), and XV_HdmiRx1_FrlModeEnable().

u32 XV_HdmiRx1_FrlDdcReadField ( XV_HdmiRx1 *  InstancePtr,
XV_HdmiRx1_FrlScdcFieldType  Field 
)

This function reads the specified FRL SCDC Field.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Fieldspecifies the fields from SCDC channels to be written
Valuespecifies the values to be written
Returns
  • XST_SUCCESS
  • XST_FAILURE
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1_FrlScdcField::Offset, XV_HDMIRX1_FRL_SCDC_ADDR_MASK, XV_HDMIRX1_FRL_SCDC_DAT_SHIFT, XV_HDMIRX1_FRL_SCDC_OFFSET, XV_HDMIRX1_FRL_SCDC_RD_MASK, XV_HDMIRX1_FRL_SCDC_RDY_MASK, XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_FrlDdcWriteField(), XV_HdmiRx1_GetFrlLtpDetection(), XV_HdmiRx1_RetrieveFrlRateLanes(), and XV_HdmiRx1_UpdateEdFlags().

int XV_HdmiRx1_FrlDdcWriteField ( XV_HdmiRx1 *  InstancePtr,
XV_HdmiRx1_FrlScdcFieldType  Field,
u8  Value 
)

This function writes the specified FRL SCDC Field.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Fieldspecifies the fields from SCDC channels to be written
Valuespecifies the values to be written
Returns
  • XST_SUCCESS
  • XST_FAILURE
  • XST_DEVICE_BUSY
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1_FrlScdcField::Mask, XV_HdmiRx1_FrlScdcField::Shift, XV_HDMIRX1_FRL_SCDC_ADDR_MASK, XV_HDMIRX1_FRL_SCDC_DAT_MASK, XV_HDMIRX1_FRL_SCDC_DAT_SHIFT, XV_HDMIRX1_FRL_SCDC_OFFSET, XV_HDMIRX1_FRL_SCDC_RDY_MASK, XV_HDMIRX1_FRL_SCDC_WR_MASK, XV_HdmiRx1_FrlDdcReadField(), XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize(), XV_HdmiRx1_FrlReset(), XV_HdmiRx1_SetFrlLtpDetection(), and XV_HdmiRx1_UpdateEdFlags().

void XV_HdmiRx1_FrlLinkRetrain ( XV_HdmiRx1 *  InstancePtr,
u8  LtpThreshold,
XV_HdmiRx1_FrlLtp  DefaultLtp 
)

This function initiates FRL rate dropping procedure.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
LtpThresholdspecifies the number of times the LTP matching module must match against the incoming link training pattern before a match is indicated
DefaultLtpspecify the link training pattern which will be used for link training purposes
  • XV_HDMIRX1_LTP_LFSR0
  • XV_HDMIRX1_LTP_LFSR1
  • XV_HDMIRX1_LTP_LFSR2
  • XV_HDMIRX1_LTP_LFSR3
Returns
Status on if FrlTraining can be started or not.
Note
None.

References XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Frl::Ltp, XV_HdmiRx1::Stream, XV_HdmiRx1_Frl::TrainingState, XV_HdmiRx1_ExecFrlState(), and XV_HdmiRx1_SetFrlLtpThreshold().

void XV_HdmiRx1_FrlLtpDetectionDisable ( XV_HdmiRx1 *  InstancePtr)

This function disables the LTP detection module.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_FrlLtpDetectionEnable ( XV_HdmiRx1 *  InstancePtr)

This function enables the LTP detection module.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_CLR_OFFSET, XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_FrlModeEnable ( XV_HdmiRx1 *  InstancePtr,
u8  LtpThreshold,
XV_HdmiRx1_FrlLtp  DefaultLtp,
u8  FfeSuppFlag 
)

This function enables the FRL mode.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
LtpThresholdspecifies the number of times the LTP matching module must match against the incoming link training pattern before a match is indicated
DefaultLtpspecify the link training pattern which will be used for link training purposes
  • XV_HDMIRX1_LTP_LFSR0
  • XV_HDMIRX1_LTP_LFSR1
  • XV_HDMIRX1_LTP_LFSR2
  • XV_HDMIRX1_LTP_LFSR3
Returns
Status on if FrlTraining can be started or not.
Note
None.

References XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Frl::FfeSuppFlag, XV_HdmiRx1::Stream, XV_HdmiRx1_Frl::TrainingState, XV_HdmiRx1_ExecFrlState(), and XV_HdmiRx1_SetFrlLtpThreshold().

void XV_HdmiRx1_FrlReset ( XV_HdmiRx1 *  InstancePtr,
u8  Reset 
)

This function resets the FRL peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies if the FRL peripheral is under reset or not.
  • 0 = Reset released
  • 1 = Reset asserted
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_CLR_OFFSET, XV_HDMIRX1_FRL_CTRL_RSTN_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, XV_HdmiRx1_FrlDdcWriteField(), and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize(), and XV_HdmiRx1_SetHpd().

u32 XV_HdmiRx1_GetFrlActivePixRatio ( XV_HdmiRx1 *  InstancePtr)

This function provides FRL Ratio (Active Pixel)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
FRL Clock Ratio (Active Pixel)
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_RATIO_ACT_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_DebugInfo().

u32 XV_HdmiRx1_GetFrlLtpDetection ( XV_HdmiRx1 *  InstancePtr,
u8  Lane 
)

This function returns the link training pattern to be detected for the selected lane.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Lanespecifies the lane of which the Link Training Pattern will be returned.
Returns
Link Training Pattern
  • 5 = LTP5 / LFSR 0
  • 6 = LTP6 / LFSR 1
  • 7 = LTP7 / LFSR 2
  • 8 = LTP8 / LFSR 3
Note
None.

References XV_HdmiRx1_FrlDdcReadField().

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

u32 XV_HdmiRx1_GetFrlTotalPixRatio ( XV_HdmiRx1 *  InstancePtr)

This function provides FRL Ratio (Total Pixel)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
FRL Clock Ratio (Total Pixel)
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_RATIO_TOT_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_DebugInfo().

u32 XV_HdmiRx1_GetPatternsMatchStatus ( XV_HdmiRx1 *  InstancePtr)

This function returns the status of the patterns matched lanes.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_MASK, XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_SHIFT, XV_HDMIRX1_FRL_STA_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_PhyResetPoll().

void XV_HdmiRx1_PhyResetPoll ( XV_HdmiRx1 *  InstancePtr)

This function polls the pattern matching status and decide if the Phy needs to be reset or not.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Frl::Lanes, XV_HdmiRx1::PhyResetCallback, XV_HdmiRx1::PhyResetRef, XV_HdmiRx1::Stream, XV_HdmiRx1_GetPatternsMatchStatus(), and XV_HdmiRx1_TmrStartMs().

void XV_HdmiRx1_ResetFrlLtpDetection ( XV_HdmiRx1 *  InstancePtr)

This function reset the link training pattern for the specified lane.

This is needed whenever the link training pattern is changed or the RxFFE is changed.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Lanespecifies the lane of which the Link Training Pattern will be detected for.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_CLR_OFFSET, XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

int XV_HdmiRx1_RetrieveFrlRateLanes ( XV_HdmiRx1 *  InstancePtr)

This function updates the software's FRL Rate and FRL Lanes by reading and decoding the information from the RX core.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Frl::CurFrlRate, XV_HdmiRx1_Frl::Lanes, XV_HdmiRx1_Frl::LineRate, XV_HdmiRx1::Stream, and XV_HdmiRx1_FrlDdcReadField().

void XV_HdmiRx1_SetFrl10MicroSecondsTimer ( XV_HdmiRx1 *  InstancePtr)

This function sets the timer of RX Core's FRL peripheral for 10 Microseconds.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
None.
Returns
None.
Note
None.

References XV_HdmiRx1::Config, and XV_HdmiRx1_Tmr1Start.

void XV_HdmiRx1_SetFrlLtpDetection ( XV_HdmiRx1 *  InstancePtr,
u8  Lane,
XV_HdmiRx1_FrlLtpType  Ltp 
)

This function sets the link training pattern to be detected for the selected lane.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Lanespecifies the lane of which the Link Training Pattern will be detected for.
Ltpspecifies Link Training Pattern
  • 5 = LTP5 / LFSR 0
  • 6 = LTP6 / LFSR 1
  • 7 = LTP7 / LFSR 2
  • 8 = LTP8 / LFSR 3
Returns
Note
None.

References XV_HdmiRx1_FrlDdcWriteField().

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

void XV_HdmiRx1_SetFrlLtpThreshold ( XV_HdmiRx1 *  InstancePtr,
u8  Threshold 
)

This function sets the number of times the full link training patterns need to be matched before it is considered as a lock.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Thresholdspecifies the number of times the full link training patterns need to be matched.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_FLT_THRES_MASK, XV_HDMIRX1_FRL_CTRL_FLT_THRES_SHIFT, XV_HDMIRX1_FRL_CTRL_OFFSET, XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_FrlLinkRetrain(), and XV_HdmiRx1_FrlModeEnable().

void XV_HdmiRx1_SetFrlRateWrEvent_En ( XV_HdmiRx1 *  InstancePtr)

This function sets the FRL rate write enable Event.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_FRL_RATE_WR_EVT_EN_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize().

Variable Documentation

const XV_HdmiRx1_FrlScdcField FrlScdcField[XV_HDMIRX1_SCDCFIELD_SIZE]

This table contains the attributes for SCDC fields Each entry consists of: 1) Register Offset 2) Bits Mask 3) Bits Shift.

const u16 FrlTimeoutLts3[4]
Initial value:
= {
180,
90,
60,
45
}

This table contains the timeout period of LTS3 for different FFE Levels in Milliseconds.