v_hdmirx1
Vitis Drivers API Documentation
xv_hdmirx1.h File Reference

Overview

This is the main header file for Xilinx HDMI RX core.

HDMI RX core is used for extracting the video and audio streams from HDMI stream. It consists of

  • Receiver core
  • AXI4-Stream to Video Bridge
  • Video Timing Controller and
  • High-bandwidth Digital Content Protection (HDCP) (Optional)
  • Data Recovery Unit (DRU) (Optional).

Receiver core performs following operations:

  • Aligns incoming data stream to the word boundary and removes inter channel skew.
  • Unscrambles the data if data rates above the 3.4 Gps. Otherwise bypasses the Scrambler.
  • Splits the data stream into video and packet data streams.
  • Optional data streams decrypt by an external HDCP module.
  • Decodes TMDS data into video data.
  • Converts the pixel data from the link domain into the video domain.

AXI Video Bridge converts the captured native video to AXI stream and outputs the video data through the AXI video interface.

Video Timing Controller (VTC) measures the video timing.

Data Recovery Unit (DRU) to recover the data from the HDMI stream if incoming HDMI stream is too slow for the transceiver.

Core Features

For a full description of HDMI RX features, please see the hardware specification.

Software Initialization & Configuration

The application needs to do following steps in order for preparing the HDMI RX core to be ready.

  • Call XV_HdmiRx1_LookupConfig using a device ID to find the core configuration.
  • Call XV_HdmiRx1_CfgInitialize to initialize the device and the driver instance associated with it.

Interrupts

This driver provides interrupt handlers

  • XV_HdmiRx1_IntrHandler, for handling the interrupts from the HDMI RX core peripherals.

Application developer needs to register interrupt handler with the processor, within their examples. Whenever processor calls registered application's interrupt handler associated with interrupt id, application's interrupt handler needs to call appropriate peripheral interrupt handler reading peripheral's Status register.

This driver provides XV_HdmiRx1_SetCallback API to register functions with HDMI RX core instance.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The HDMI RX driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

MODIFICATION HISTORY:
Ver   Who    Date     Changes


1.00 EB 02/05/19 Initial release.

Data Structures

struct  XV_HdmiRx1_Config
 This typedef contains configuration information for the HDMI RX core. More...
 
struct  XV_HdmiRx1_AudioStream
 This typedef contains HDMI RX audio stream specific data structure. More...
 
struct  XV_HdmiRx1_Stream
 This typedef contains HDMI RX stream specific data structure. More...
 
struct  XV_HdmiRx1_DynHDR_Info
 This typedef contains HDMI RX stream specific Dynamic HDR info. More...
 
struct  XV_HdmiRx1
 The XHdmiRx1 driver instance data. More...
 

Macros

#define XV_HDMIRX1_H_
 Prevent circular inclusions by using protection macros. More...
 

Enumerations

Handler Types
enum  XV_HdmiRx1_HandlerType {
  XV_HDMIRX1_HANDLER_CONNECT = 1, XV_HDMIRX1_HANDLER_BRDG_OVERFLOW, XV_HDMIRX1_HANDLER_AUX, XV_HDMIRX1_HANDLER_AUD,
  XV_HDMIRX1_HANDLER_LNKSTA, XV_HDMIRX1_HANDLER_DDC, XV_HDMIRX1_HANDLER_STREAM_DOWN, XV_HDMIRX1_HANDLER_STREAM_INIT,
  XV_HDMIRX1_HANDLER_STREAM_UP, XV_HDMIRX1_HANDLER_HDCP, XV_HDMIRX1_HANDLER_DDC_HDCP_14_PROT, XV_HDMIRX1_HANDLER_DDC_HDCP_22_PROT,
  XV_HDMIRX1_HANDLER_LINK_ERROR, XV_HDMIRX1_HANDLER_SYNC_LOSS, XV_HDMIRX1_HANDLER_MODE, XV_HDMIRX1_HANDLER_TMDS_CLK_RATIO,
  XV_HDMIRX1_HANDLER_VIC_ERROR, XV_HDMIRX1_HANDLER_PHY_RESET, XV_HDMIRX1_HANDLER_LNK_RDY_ERR, XV_HDMIRX1_HANDLER_VID_RDY_ERR,
  XV_HDMIRX1_HANDLER_SKEW_LOCK_ERR, XV_HDMIRX1_HANDLER_FRL_CONFIG, XV_HDMIRX1_HANDLER_FRL_START, XV_HDMIRX1_HANDLER_TMDS_CONFIG ,
  XV_HDMIRX1_HANDLER_VFP_CHANGE, XV_HDMIRX1_HANDLER_VRR_RDY, XV_HDMIRX1_HANDLER_DYN_HDR, XV_HDMIRX1_HANDLER_DSC_STRM_CH,
  XV_HDMIRX1_HANDLER_DSC_PKT_ERR, XV_HDMIRX1_HANDLER_DSC_STS_UPDT
}
 These constants specify different types of handler and used to differentiate interrupt requests from peripheral. More...
 
HDMI RX stream status
enum  XV_HdmiRx1_State { ,
  XV_HDMIRX1_STATE_STREAM_DOWN, XV_HDMIRX1_STATE_STREAM_IDLE, XV_HDMIRX1_STATE_STREAM_INIT, XV_HDMIRX1_STATE_STREAM_ARM,
  XV_HDMIRX1_STATE_STREAM_LOCK, XV_HDMIRX1_STATE_STREAM_RDY, XV_HDMIRX1_STATE_STREAM_UP
}
 
HDMI RX sync status
enum  XV_HdmiRx1_SyncStatus { XV_HDMIRX1_SYNCSTAT_SYNC_LOSS, XV_HDMIRX1_SYNCSTAT_SYNC_EST }
 
HDMI RX audio format
enum  XV_HdmiRx1_AudioFormatType
 
HDMI RX EDID RAM Size
enum  XV_HdmiRx1_EdidSize
 

HDMI RX Dynamic HDR Error type

#define TIME_10MS   (XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ/100)
 
#define TIME_200MS   (XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ/5)
 
#define TIME_16MS   ((XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ*10)/625)
 
#define TIME_500MS   (XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ / 2)
 
#define XV_HdmiRx1_GetTime10Ms(InstancePtr)   (InstancePtr)->Config.AxiLiteClkFreq/100
 This macro returns the clock cycles required to count up to 10Ms with respect to AXI Lite Frequency. More...
 
#define XV_HdmiRx1_GetTime16Ms(InstancePtr)   ((InstancePtr)->Config.AxiLiteClkFreq * 10) / 625
 This macro returns the clock cycles required to count up to 16Ms with respect to AXI Lite Frequency. More...
 
#define XV_HdmiRx1_GetTime200Ms(InstancePtr)   (InstancePtr)->Config.AxiLiteClkFreq/5
 This macro returns the clock cycles required to count up to 200Ms with respect to AXI Lite Frequency. More...
 
#define XV_HdmiRx1_GetTime1S(InstancePtr)   (InstancePtr)->Config.AxiLiteClkFreq
 This macro returns the clock cycles required to count up to 1s with respect to AXI Lite Frequency. More...
 
#define XV_HdmiRx1_GetVersion(InstancePtr)
 This macro reads the RX version. More...
 
#define XV_HdmiRx1_Reset(InstancePtr, Reset)
 This macro asserts or clears the HDMI RX reset. More...
 
#define XV_HdmiRx1_LinkEnable(InstancePtr, SetClr)
 This macro asserts or clears the HDMI RX link enable. More...
 
#define XV_HdmiRx1_VideoEnable(InstancePtr, SetClr)
 This macro asserts or clears the HDMI RX video enable. More...
 
#define XV_HdmiRx1_SetScrambler(InstancePtr, SetClr)
 This macro controls the HDMI RX Scrambler. More...
 
#define XV_HdmiRx1_Bridge_yuv420(InstancePtr, SetClr)
 This macro controls the YUV420 mode for video bridge. More...
 
#define XV_HdmiRx1_Bridge_pixel(InstancePtr, SetClr)
 This macro controls the Pixel Drop mode for video bridge. More...
 
#define XV_HdmiRx1_AxisEnable(InstancePtr, Enable)
 This macro asserts or clears the AXIS enable output port. More...
 
#define XV_HdmiRx1_PioEnable(InstancePtr)
 This macro enables the HDMI RX PIO peripheral. More...
 
#define XV_HdmiRx1_PioDisable(InstancePtr)
 This macro disables the HDMI RX PIO peripheral. More...
 
#define XV_HdmiRx1_PioIntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX PIO peripheral. More...
 
#define XV_HdmiRx1_PioIntrDisable(InstancePtr)
 This macro disables interrupts in the HDMI RX PIO peripheral. More...
 
#define XV_HdmiRx1_Tmr1Enable(InstancePtr)
 This macro enables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr1Disable(InstancePtr)
 This macro disables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr1IntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr1IntrDisable(InstancePtr)
 This macro disables interrupt in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr1Start(InstancePtr, Value)
 This macro starts the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_GetTmr1Value(InstancePtr)
 This macro reads the HDMI RX timer peripheral's remaining timer counter value. More...
 
#define XV_HdmiRx1_Tmr2Enable(InstancePtr)
 This macro enables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr2Disable(InstancePtr)
 This macro disables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr2IntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr2IntrDisable(InstancePtr)
 This macro disables interrupt in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr2Start(InstancePtr, Value)
 This macro starts the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_GetTmr2Value(InstancePtr)
 This macro reads the HDMI RX timer peripheral's remaining timer counter value. More...
 
#define XV_HdmiRx1_Tmr3Enable(InstancePtr)
 This macro enables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr3Disable(InstancePtr)
 This macro disables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr3IntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr3IntrDisable(InstancePtr)
 This macro disables interrupt in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr3Start(InstancePtr, Value)
 This macro starts the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_GetTmr3Value(InstancePtr)
 This macro reads the HDMI RX timer peripheral's remaining timer counter value. More...
 
#define XV_HdmiRx1_Tmr4Enable(InstancePtr)
 This macro enables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr4Disable(InstancePtr)
 This macro disables the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr4IntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr4IntrDisable(InstancePtr)
 This macro disables interrupt in the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_Tmr4Start(InstancePtr, Value)
 This macro starts the HDMI RX timer peripheral. More...
 
#define XV_HdmiRx1_GetTmr4Value(InstancePtr)
 This macro reads the HDMI RX timer peripheral's remaining timer counter value. More...
 
#define XV_HdmiRx1_VtdEnable(InstancePtr)
 This macro enables the HDMI RX Timing Detector peripheral. More...
 
#define XV_HdmiRx1_VtdDisable(InstancePtr)
 This macro disables the HDMI RX Timing Detector peripheral. More...
 
#define XV_HdmiRx1_VtdIntrEnable(InstancePtr)
 This macro enables interrupt in the HDMI RX Timing Detector peripheral. More...
 
#define XV_HdmiRx1_VtdIntrDisable(InstancePtr)
 This macro disables interrupt in the HDMI RX Timing Detector peripheral. More...
 
#define XV_HdmiRx1_VtdVfpEvent(InstancePtr, SetClr)
 This macro allow control to enable/disable the HDMI RX VFP event. More...
 
#define XV_HdmiRx1_VtdSetTimebase(InstancePtr, Value)
 This macro sets the timebase in the HDMI RX Timing Detector peripheral. More...
 
#define XV_HdmiRx1_DdcEnable(InstancePtr)
 This macro enables the HDMI RX Display Data Channel (DDC) peripheral. More...
 
#define XV_HdmiRx1_DdcScdcEnable(InstancePtr)
 This macro enables the SCDC in the DDC peripheral. More...
 
#define XV_HdmiRx1_DdcHdcpEnable(InstancePtr)
 This macro enables the HDCP in the DDC peripheral. More...
 
#define XV_HdmiRx1_DdcHdcpDisable(InstancePtr)
 
#define XV_HdmiRx1_DdcHdcp14Mode(InstancePtr)
 This macro sets the DDC peripheral into HDCP 1.4 mode. More...
 
#define XV_HdmiRx1_DdcHdcp22Mode(InstancePtr)
 This macro sets the DDC peripheral into HDCP 2.2 mode. More...
 
#define XV_HdmiRx1_DdcDisable(InstancePtr)
 This macro disables the HDMI RX Display Data Channel (DDC) peripheral. More...
 
#define XV_HdmiRx1_DdcIntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX Display Data Channel (DDC) peripheral. More...
 
#define XV_HdmiRx1_DdcIntrDisable(InstancePtr)
 This macro disables interrupts in the HDMI RX Display Data Channel (DDC) peripheral. More...
 
#define XV_HdmiRx1_DdcScdcClear(InstancePtr)
 This macro clears the SCDC registers in the DDC peripheral. More...
 
#define XV_HdmiRx1_AuxEnable(InstancePtr)
 This macro enables the HDMI RX Auxiliary (AUX) peripheral. More...
 
#define XV_HdmiRx1_AuxDisable(InstancePtr)
 This macro disables the HDMI RX Auxiliary (AUX) peripheral. More...
 
#define XV_HdmiRx1_AuxIntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX Auxiliary (AUX) peripheral. More...
 
#define XV_HdmiRx1_AuxIntrDisable(InstancePtr)
 This macro disables interrupts in the HDMI RX Auxiliary (AUX) peripheral. More...
 
#define XV_HdmiRx1_AuxFSyncVrrChEvtEnable(InstancePtr)
 This macro enables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral. More...
 
#define XV_HdmiRx1_AuxFSyncVrrChEvtDisable(InstancePtr)
 This macro disables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral. More...
 
#define XV_HdmiRx1_AudioEnable(InstancePtr)
 This macro enables the HDMI RX Audio (AUD) peripheral. More...
 
#define XV_HdmiRx1_AudioDisable(InstancePtr)
 This macro disables the HDMI RX Audio (AUD) peripheral. More...
 
#define XV_HdmiRx1_AudioIntrEnable(InstancePtr)
 This macro enables interrupts in the HDMI RX Audio (AUD) peripheral. More...
 
#define XV_HdmiRx1_AudioIntrDisable(InstancePtr)
 This macro disables interrupts in the HDMI RX Audio (AUD) peripheral. More...
 
#define XV_HdmiRx1_SetAudioAcrUpdateEventEn(InstancePtr)
 This macro enables ACR Update Event in the HDMI RX Audio (AUD) peripheral. More...
 
#define XV_HdmiRx1_ClearAudioAcrUpdateEventEn(InstancePtr)
 This macro disables ACR Update Event in the HDMI RX Audio (AUD) peripheral. More...
 
#define XV_HdmiRx1_LnkstaEnable(InstancePtr)
 This macro enables the HDMI RX Link Status (LNKSTA) peripheral. More...
 
#define XV_HdmiRx1_LnkstaDisable(InstancePtr)
 This macro disables the HDMI RX Link Status (LNKSTA) peripheral. More...
 
#define XV_HdmiRx1_LinkIntrEnable(InstancePtr)
 This macro enables interrupt in the HDMI RX Link Status (LNKSTA) peripheral. More...
 
#define XV_HdmiRx1_LinkIntrDisable(InstancePtr)
 This macro disable interrupt in the HDMI RX Link Status (LNKSTA) peripheral. More...
 
#define XV_HdmiRx1_IsAudioActive(InstancePtr)   (InstancePtr)->Stream.Audio.Active
 This macro returns true is the audio stream is active else false. More...
 
#define XV_HdmiRx1_GetAudioChannels(InstancePtr)   (InstancePtr)->Stream.Audio.Channels
 This macro returns the number of active audio channels. More...
 
#define XV_HdmiRx1_DdcHdcpClearWriteMessageBuffer(InstancePtr)
 This macro clears the HDCP write message buffer in the DDC peripheral. More...
 
#define XV_HdmiRx1_DdcHdcpClearReadMessageBuffer(InstancePtr)
 This macro clears the HDCP read message buffer in the DDC peripheral. More...
 
#define XV_HdmiRx1_DynHDR_DM_Enable(InstancePtr)
 This macro enables the data mover for Dynamic HDR. More...
 
#define XV_HdmiRx1_DynHDR_DM_Disable(InstancePtr)
 This macro disables the data mover for Dynamic HDR. More...
 
enum  XV_HdmiRx1_DynHdrErrType
 
typedef void(* XV_HdmiRx1_Callback )(void *CallbackRef)
 Callback type for interrupt. More...
 
typedef void(* XV_HdmiRx1_HdcpCallback )(void *CallbackRef, int Data)
 
XV_HdmiRx1_ConfigXV_HdmiRx1_LookupConfig (u16 DeviceId)
 This function returns a reference to an XV_HdmiRx1_Config structure based on the core id, DeviceId. More...
 
int XV_HdmiRx1_CfgInitialize (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_Config *CfgPtr, UINTPTR EffectiveAddr)
 This function initializes the HDMI RX core. More...
 
void XV_HdmiRx1_SetAxiClkFreq (XV_HdmiRx1 *InstancePtr, u32 ClkFreq)
 This function sets the AXI4-Lite Clock Frequency. More...
 
void XV_HdmiRx1_Clear (XV_HdmiRx1 *InstancePtr)
 This function clears the HDMI RX variables and sets them to the defaults. More...
 
int XV_HdmiRx1_SetStream (XV_HdmiRx1 *InstancePtr, XVidC_PixelsPerClock Ppc, u32 Clock)
 This function sets the HDMI RX stream parameters. More...
 
int XV_HdmiRx1_IsStreamUp (XV_HdmiRx1 *InstancePtr)
 This function provides status of the stream. More...
 
int XV_HdmiRx1_IsStreamScrambled (XV_HdmiRx1 *InstancePtr)
 This function provides the stream scrambler status. More...
 
int XV_HdmiRx1_IsStreamConnected (XV_HdmiRx1 *InstancePtr)
 This function provides the stream connected status. More...
 
int XV_HdmiRx1_SetHpd (XV_HdmiRx1 *InstancePtr, u8 SetClr)
 This function enables/clear Hot-Plug-Detect. More...
 
void XV_HdmiRx1_INT_VRST (XV_HdmiRx1 *InstancePtr, u8 Reset)
 This function asserts or releases the HDMI RX Internal VRST. More...
 
void XV_HdmiRx1_INT_LRST (XV_HdmiRx1 *InstancePtr, u8 Reset)
 This function asserts or releases the HDMI RX Internal LRST. More...
 
void XV_HdmiRx1_EXT_VRST (XV_HdmiRx1 *InstancePtr, u8 Reset)
 This function asserts or releases the HDMI RX External VRST. More...
 
void XV_HdmiRx1_EXT_SYSRST (XV_HdmiRx1 *InstancePtr, u8 Reset)
 This function asserts or releases the HDMI RX External SYSRST. More...
 
int XV_HdmiRx1_SetPixelRate (XV_HdmiRx1 *InstancePtr)
 This function sets the pixel rate. More...
 
void XV_HdmiRx1_SetColorFormat (XV_HdmiRx1 *InstancePtr)
 This function sets the color format. More...
 
int XV_HdmiRx1_IsLinkStatusErrMax (XV_HdmiRx1 *InstancePtr)
 This function provides status of one of the link error counters reached the maximum value. More...
 
void XV_HdmiRx1_ClearLinkStatus (XV_HdmiRx1 *InstancePtr)
 This function clears the link error counters. More...
 
u32 XV_HdmiRx1_GetLinkStatus (XV_HdmiRx1 *InstancePtr, u8 Type)
 This function provides status of the HDMI RX core Link Status peripheral. More...
 
u32 XV_HdmiRx1_GetAcrCts (XV_HdmiRx1 *InstancePtr)
 This function provides audio clock regenerating CTS (Cycle-Time Stamp) value at the HDMI sink device. More...
 
u32 XV_HdmiRx1_GetAcrN (XV_HdmiRx1 *InstancePtr)
 This function provides audio clock regenerating factor N value. More...
 
int XV_HdmiRx1_DdcLoadEdid (XV_HdmiRx1 *InstancePtr, u8 *Data, u16 Length)
 This function loads the EDID data into the DDC slave. More...
 
void XV_HdmiRx1_DdcHdcpSetAddress (XV_HdmiRx1 *InstancePtr, u32 Addr)
 This function sets the HDCP address in the DDC peripheral. More...
 
void XV_HdmiRx1_DdcHdcpWriteData (XV_HdmiRx1 *InstancePtr, u32 Data)
 This function writes HDCP data in the DDC peripheral. More...
 
u32 XV_HdmiRx1_DdcHdcpReadData (XV_HdmiRx1 *InstancePtr)
 This function reads HDCP data from the DDC peripheral. More...
 
u16 XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords (XV_HdmiRx1 *InstancePtr)
 This function gets the number of bytes of the HDCP 2.2 write buffer in the DDC slave. More...
 
int XV_HdmiRx1_DdcIsHdcpWriteMessageBufferEmpty (XV_HdmiRx1 *InstancePtr)
 This function returns the status of the HDCP 2.2 write buffer in the DDC slave. More...
 
u16 XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords (XV_HdmiRx1 *InstancePtr)
 This function gets the number of bytes of the HDCP 2.2 read buffer in the DDC slave. More...
 
int XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty (XV_HdmiRx1 *InstancePtr)
 This function returns the status of the HDCP 2.2 read message buffer in the DDC slave. More...
 
int XV_HdmiRx1_GetTmdsClockRatio (XV_HdmiRx1 *InstancePtr)
 This function gets the SCDC TMDS clock ratio bit. More...
 
u8 XV_HdmiRx1_GetAviVic (XV_HdmiRx1 *InstancePtr)
 This function returns the AVI VIC (captured by the AUX peripheral) More...
 
XVidC_ColorFormat XV_HdmiRx1_GetAviColorSpace (XV_HdmiRx1 *InstancePtr)
 This function returns the AVI colorspace (captured by the AUX peripheral) More...
 
XVidC_ColorDepth XV_HdmiRx1_GetGcpColorDepth (XV_HdmiRx1 *InstancePtr)
 This function returns the GCP color depth (captured by the AUX peripheral) More...
 
int XV_HdmiRx1_GetVideoProperties (XV_HdmiRx1 *InstancePtr)
 This function reads the video properties from the aux peripheral. More...
 
int XV_HdmiRx1_GetVideoTiming (XV_HdmiRx1 *InstancePtr)
 This function reads the video timing from the VTD peripheral. More...
 
u32 XV_HdmiRx1_Divide (u32 Dividend, u32 Divisor)
 This function calculates the divider for the frame calculation. More...
 
void XV_HdmiRx1_SetPixelClk (XV_HdmiRx1 *InstancePtr)
 This function sets the PixelClk based on the current ColorDepth, RefClk and ColorFormatId. More...
 
void XV_HdmiRx1_Start (XV_HdmiRx1 *InstancePtr)
 This function starts the HDMI RX core. More...
 
void XV_HdmiRx1_Stop (XV_HdmiRx1 *InstancePtr)
 This function stops the HDMI RX core. More...
 
void XV_HdmiRx1_UpdateEdFlags (XV_HdmiRx1 *InstancePtr)
 This function checks if RX's CED or RSED counters are incrementing at the rate of 4 or higher per second or if they first hit the maximum value (0x7FFF) then set the CED_Update or RSED_Update SCDC flags if true. More...
 
void XV_HdmiRx1_TmrStartMs (XV_HdmiRx1 *InstancePtr, u32 Milliseconds, u8 TimerSelect)
 This function sets the timer of RX Core. More...
 
XVidC_VideoMode XV_HdmiRx1_LookupVmId (u8 Vic)
 This function searches for the video mode based on the vic. More...
 
void XV_HdmiRx1_ParseSrcProdDescInfoframe (XV_HdmiRx1 *InstancePtr)
 
void XV_HdmiRx1_ParseVideoTimingExtMetaIF (XV_HdmiRx1 *InstancePtr)
 
void XV_HdmiRx1_FrlModeEnable (XV_HdmiRx1 *InstancePtr, u8 LtpThreshold, XV_HdmiRx1_FrlLtp DefaultLtp, u8 FfeSuppFlag)
 This function enables the FRL mode. More...
 
int XV_HdmiRx1_ExecFrlState (XV_HdmiRx1 *InstancePtr)
 This function executes the different of states of FRL. More...
 
u32 XV_HdmiRx1_GetPatternsMatchStatus (XV_HdmiRx1 *InstancePtr)
 This function returns the status of the patterns matched lanes. More...
 
void XV_HdmiRx1_PhyResetPoll (XV_HdmiRx1 *InstancePtr)
 This function polls the pattern matching status and decide if the Phy needs to be reset or not. More...
 
void XV_HdmiRx1_FrlLinkRetrain (XV_HdmiRx1 *InstancePtr, u8 LtpThreshold, XV_HdmiRx1_FrlLtp DefaultLtp)
 This function initiates FRL rate dropping procedure. More...
 
void XV_HdmiRx1_FrlReset (XV_HdmiRx1 *InstancePtr, u8 Reset)
 This function resets the FRL peripheral. More...
 
int XV_HdmiRx1_ConfigFrlLtpDetection (XV_HdmiRx1 *InstancePtr)
 This function configures the link training pattern to be detected. More...
 
void XV_HdmiRx1_SetFrlLtpDetection (XV_HdmiRx1 *InstancePtr, u8 Lane, XV_HdmiRx1_FrlLtpType Ltp)
 This function sets the link training pattern to be detected for the selected lane. More...
 
u32 XV_HdmiRx1_GetFrlLtpDetection (XV_HdmiRx1 *InstancePtr, u8 Lane)
 This function returns the link training pattern to be detected for the selected lane. More...
 
void XV_HdmiRx1_ResetFrlLtpDetection (XV_HdmiRx1 *InstancePtr)
 This function reset the link training pattern for the specified lane. More...
 
void XV_HdmiRx1_FrlLtpDetectionEnable (XV_HdmiRx1 *InstancePtr)
 This function enables the LTP detection module. More...
 
void XV_HdmiRx1_FrlLtpDetectionDisable (XV_HdmiRx1 *InstancePtr)
 This function disables the LTP detection module. More...
 
void XV_HdmiRx1_SetFrlLtpThreshold (XV_HdmiRx1 *InstancePtr, u8 Threshold)
 This function sets the number of times the full link training patterns need to be matched before it is considered as a lock. More...
 
int XV_HdmiRx1_RetrieveFrlRateLanes (XV_HdmiRx1 *InstancePtr)
 This function updates the software's FRL Rate and FRL Lanes by reading and decoding the information from the RX core. More...
 
void XV_HdmiRx1_SetFrlRateWrEvent_En (XV_HdmiRx1 *InstancePtr)
 This function sets the FRL rate write enable Event. More...
 
int XV_HdmiRx1_FrlDdcWriteField (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)
 This function writes the specified FRL SCDC Field. More...
 
u32 XV_HdmiRx1_FrlDdcReadField (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field)
 This function reads the specified FRL SCDC Field. More...
 
void XV_HdmiRx1_SetFrlFltNoTimeout (XV_HdmiRx1 *InstancePtr)
 
void XV_HdmiRx1_ClearFrlFltNoTimeout (XV_HdmiRx1 *InstancePtr)
 
void XV_HdmiRx1_SetFrl10MicroSecondsTimer (XV_HdmiRx1 *InstancePtr)
 This function sets the timer of RX Core's FRL peripheral for 10 Microseconds. More...
 
u32 XV_HdmiRx1_GetFrlTotalPixRatio (XV_HdmiRx1 *InstancePtr)
 This function provides FRL Ratio (Total Pixel) More...
 
u32 XV_HdmiRx1_GetFrlActivePixRatio (XV_HdmiRx1 *InstancePtr)
 This function provides FRL Ratio (Active Pixel) More...
 
void XV_HdmiRx1_RestartFrlLt (XV_HdmiRx1 *InstancePtr)
 
void XV_HdmiRx1_FrlFltUpdate (XV_HdmiRx1 *InstancePtr, u8 Flag)
 
void XV_HdmiRx1_Info (XV_HdmiRx1 *InstancePtr)
 This function prints stream and timing information on STDIO/UART console. More...
 
void XV_HdmiRx1_DebugInfo (XV_HdmiRx1 *InstancePtr)
 This function prints debug information on STDIO/UART console. More...
 
void XV_HdmiRx1_RegisterDebug (XV_HdmiRx1 *InstancePtr)
 This function prints out HDMI RX register. More...
 
void XV_HdmiRx1_DdcRegDump (XV_HdmiRx1 *InstancePtr)
 This function prints out RX's SCDC registers and values on STDIO/UART. More...
 
int XV_HdmiRx1_SelfTest (XV_HdmiRx1 *InstancePtr)
 This function reads ID of PIO peripheral. More...
 
void XV_HdmiRx1_IntrHandler (void *InstancePtr)
 This function is the interrupt handler for the HDMI RX driver. More...
 
int XV_HdmiRx1_SetCallback (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_HandlerType HandlerType, void *CallbackFunc, void *CallbackRef)
 This function installs an asynchronous callback function for the given HandlerType: More...
 
XV_HdmiC_VideoTimingExtMeta * XV_HdmiRx1_GetVidTimingExtMeta (XV_HdmiRx1 *InstancePtr)
 
XV_HdmiC_SrcProdDescIF * XV_HdmiRx1_GetSrcProdDescIF (XV_HdmiRx1 *InstancePtr)
 
XV_HdmiC_VrrInfoframeType XV_HdmiRx1_GetVrrIfType (XV_HdmiRx1 *InstancePtr)
 This function returns VRR infoframe type. More...
 
void XV_HdmiRx1_SetVrrIfType (XV_HdmiRx1 *InstancePtr, XV_HdmiC_VrrInfoframeType Type)
 This function Sets VRR infoframe type. More...
 
void XV_HdmiRx1_DynHDR_SetAddr (XV_HdmiRx1 *InstancePtr, u64 Addr)
 This function sets the Dynamic HDR buffer address. More...
 
void XV_HdmiRx1_DynHDR_GetInfo (XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_DynHDR_Info *RxDynInfoPtr)
 This function gets the Dynamic HDR packet type, length, whether graphics overlay and errors if any. More...
 
u32 XV_HdmiRx1_DSC_IsEnableStream (XV_HdmiRx1 *InstancePtr)
 
int XV_HdmiRx1_DSC_SetDecodeFail (XV_HdmiRx1 *InstancePtr)
 
int XV_HdmiRx1_DSC_SetDscFrlMax (XV_HdmiRx1 *InstancePtr)
 

Macro Definition Documentation

#define XV_HdmiRx1_AudioDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_AUD_CTRL_RUN_MASK
AUD Control Run mask.
Definition: xv_hdmirx1_hw.h:426
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET
AUD Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:420

This macro disables the HDMI RX Audio (AUD) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AudioDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_AudioEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_AUD_CTRL_RUN_MASK
AUD Control Run mask.
Definition: xv_hdmirx1_hw.h:426
#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET
AUD Control Register Set offset.
Definition: xv_hdmirx1_hw.h:419
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables the HDMI RX Audio (AUD) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AudioEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_AudioIntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET
AUD Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:420
#define XV_HDMIRX1_AUD_CTRL_IE_MASK
AUD Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:427

This macro disables interrupts in the HDMI RX Audio (AUD) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AudioIntrDisable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_AudioIntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET
AUD Control Register Set offset.
Definition: xv_hdmirx1_hw.h:419
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUD_CTRL_IE_MASK
AUD Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:427

This macro enables interrupts in the HDMI RX Audio (AUD) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AudioIntrEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_AuxDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_AUX_CTRL_RUN_MASK
AUX Control Run mask.
Definition: xv_hdmirx1_hw.h:324
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET
AUX Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:312

This macro disables the HDMI RX Auxiliary (AUX) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AuxDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_AuxEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_AUX_CTRL_RUN_MASK
AUX Control Run mask.
Definition: xv_hdmirx1_hw.h:324
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET
AUX Control Register Set offset.
Definition: xv_hdmirx1_hw.h:311

This macro enables the HDMI RX Auxiliary (AUX) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AuxEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_AuxFSyncVrrChEvtDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK
AUX Control FSync/VRR change event enable mask.
Definition: xv_hdmirx1_hw.h:326
#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET
AUX Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:312

This macro disables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AuxFSyncVrrChEvtDisable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_AuxFSyncVrrChEvtEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK
AUX Control FSync/VRR change event enable mask.
Definition: xv_hdmirx1_hw.h:326
#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET
AUX Control Register Set offset.
Definition: xv_hdmirx1_hw.h:311

This macro enables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AuxFSyncVrrChEvtEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_AuxIntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUX_CTRL_IE_MASK
AUX Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:325
#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET
AUX Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:312

This macro disables interrupts in the HDMI RX Auxiliary (AUX) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AuxIntrDisable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_AuxIntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET
AUX Control Register Set offset.
Definition: xv_hdmirx1_hw.h:311
#define XV_HDMIRX1_AUX_CTRL_IE_MASK
AUX Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:325

This macro enables interrupts in the HDMI RX Auxiliary (AUX) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_AuxIntrEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_AxisEnable (   InstancePtr,
  Enable 
)
Value:
{ \
if (Enable) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK
PIO Out Axis Enable mask.
Definition: xv_hdmirx1_hw.h:121
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro asserts or clears the AXIS enable output port.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies TRUE/FALSE value to either assert or release HDMI RX reset.
Returns
None.
Note
The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI link and video reset. C-style signature: void XV_HdmiRx1_AxisEnable(InstancePtr, Enable)
#define XV_HdmiRx1_Bridge_pixel (   InstancePtr,
  SetClr 
)
Value:
{ \
if (SetClr) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK
PIO Out Bridge_Pixel drop mask.
Definition: xv_hdmirx1_hw.h:129
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro controls the Pixel Drop mode for video bridge.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
SetClrspecifies TRUE/FALSE value to either enable or disable the Pixel Repitition.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Bridge_pixel(XV_HdmiRx1 *InstancePtr, u8 SetClr)
#define XV_HdmiRx1_Bridge_yuv420 (   InstancePtr,
  SetClr 
)
Value:
{ \
if (SetClr) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK
PIO Out Bridge_YUV420 mask.
Definition: xv_hdmirx1_hw.h:128
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro controls the YUV420 mode for video bridge.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
SetClrspecifies TRUE/FALSE value to either enable or disable the YUV 420 Support.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Bridge_yuv420(XV_HdmiRx1 *InstancePtr, u8 SetClr)
#define XV_HdmiRx1_ClearAudioAcrUpdateEventEn (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg(InstancePtr->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK
AUD Control ACR Update Event Enable mask.
Definition: xv_hdmirx1_hw.h:428
#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET
AUD Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:420

This macro disables ACR Update Event in the HDMI RX Audio (AUD) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.
#define XV_HdmiRx1_DdcDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_RUN_MASK
DDC Control Run mask.
Definition: xv_hdmirx1_hw.h:271
#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET
DDC Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:259
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro disables the HDMI RX Display Data Channel (DDC) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_DdcEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_RUN_MASK
DDC Control Run mask.
Definition: xv_hdmirx1_hw.h:271
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables the HDMI RX Display Data Channel (DDC) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_DdcHdcp14Mode (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET
DDC Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:259
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK
DDC Control HDCP mode mask.
Definition: xv_hdmirx1_hw.h:279

This macro sets the DDC peripheral into HDCP 1.4 mode.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcHdcp14Mode(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_DdcHdcp22Mode (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK
DDC Control HDCP mode mask.
Definition: xv_hdmirx1_hw.h:279

This macro sets the DDC peripheral into HDCP 2.2 mode.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcHdcp22Mode(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_DdcHdcpClearReadMessageBuffer (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_RMSG_CLR_MASK
DDC Control read message clear mask.
Definition: xv_hdmirx1_hw.h:278
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro clears the HDCP read message buffer in the DDC peripheral.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
None.
Note
C-style signature: void XHdmiRx1_DdcHdcpClearReadMessageBuffer(XHdmi_Rx *InstancePtr)
#define XV_HdmiRx1_DdcHdcpClearWriteMessageBuffer (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_DDC_CTRL_WMSG_CLR_MASK
DDC Control write message clear mask.
Definition: xv_hdmirx1_hw.h:277

This macro clears the HDCP write message buffer in the DDC peripheral.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
None.
Note
C-style signature: void XHdmiRx1_DdcHdcpClearWriteMessageBuffer(XHdmi_Rx *InstancePtr)
#define XV_HdmiRx1_DdcHdcpEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_HDCP_EN_MASK
DDC Control HDCP enable mask.
Definition: xv_hdmirx1_hw.h:275
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables the HDCP in the DDC peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcHdcpEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_DdcIntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_IE_MASK
DDC Control Interrupt enable mask.
Definition: xv_hdmirx1_hw.h:272
#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET
DDC Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:259
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro disables interrupts in the HDMI RX Display Data Channel (DDC) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcIntrDisable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_DdcIntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_IE_MASK
DDC Control Interrupt enable mask.
Definition: xv_hdmirx1_hw.h:272
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables interrupts in the HDMI RX Display Data Channel (DDC) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcIntrEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_DdcScdcClear (   InstancePtr)
Value:
{ \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
usleep(50);\
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
XV_HdmiRx1_FrlDdcWriteField(InstancePtr, XV_HDMIRX1_SCDCFIELD_FLT_READY,\
1);\
XV_HdmiRx1_FrlDdcWriteField(InstancePtr,XV_HDMIRX1_SCDCFIELD_SINK_VER, \
1);\
}
#define XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK
DDC Control SCDC clear mask.
Definition: xv_hdmirx1_hw.h:276
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET
DDC Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:259
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
int XV_HdmiRx1_FrlDdcWriteField(XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)
This function writes the specified FRL SCDC Field.
Definition: xv_hdmirx1_frl.c:1394

This macro clears the SCDC registers in the DDC peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcScdcClear(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_DdcScdcEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET
DDC Control Register Set offset.
Definition: xv_hdmirx1_hw.h:258
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_DDC_CTRL_SCDC_EN_MASK
DDC Control SCDC enable mask.
Definition: xv_hdmirx1_hw.h:274

This macro enables the SCDC in the DDC peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DdcScdcEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_DynHDR_DM_Disable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK
PIO Out Dynamic HDR Data Mover enable mask.
Definition: xv_hdmirx1_hw.h:147
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro disables the data mover for Dynamic HDR.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DynHDR_DM_Disable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_DynHDR_DM_Enable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK
PIO Out Dynamic HDR Data Mover enable mask.
Definition: xv_hdmirx1_hw.h:147
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro enables the data mover for Dynamic HDR.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_DynHDR_DM_Enable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_GetAudioChannels (   InstancePtr)    (InstancePtr)->Stream.Audio.Channels

This macro returns the number of active audio channels.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Number of active audio channels.
Note
C-style signature: u32 XV_HdmiRx1_GetAudioChannels(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_GetTime10Ms (   InstancePtr)    (InstancePtr)->Config.AxiLiteClkFreq/100

This macro returns the clock cycles required to count up to 10Ms with respect to AXI Lite Frequency.

Parameters
InstancePtris a pointer to the XV_HdmiRX1 core instance.
Returns
None.
#define XV_HdmiRx1_GetTime16Ms (   InstancePtr)    ((InstancePtr)->Config.AxiLiteClkFreq * 10) / 625

This macro returns the clock cycles required to count up to 16Ms with respect to AXI Lite Frequency.

Parameters
InstancePtris a pointer to the XV_HdmiRX1 core instance.
Returns
None.

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_GetTime1S (   InstancePtr)    (InstancePtr)->Config.AxiLiteClkFreq

This macro returns the clock cycles required to count up to 1s with respect to AXI Lite Frequency.

Parameters
InstancePtris a pointer to the XV_HdmiRX1 core instance.
Returns
None.
#define XV_HdmiRx1_GetTime200Ms (   InstancePtr)    (InstancePtr)->Config.AxiLiteClkFreq/5

This macro returns the clock cycles required to count up to 200Ms with respect to AXI Lite Frequency.

Parameters
InstancePtris a pointer to the XV_HdmiRX1 core instance.
Returns
None.
#define XV_HdmiRx1_GetTmr1Value (   InstancePtr)
Value:
XV_HdmiRx1_ReadReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR1_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:196
#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a HDMI RX register.
Definition: xv_hdmirx1_hw.h:783

This macro reads the HDMI RX timer peripheral's remaining timer counter value.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_GetTmr1Value(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

#define XV_HdmiRx1_GetTmr2Value (   InstancePtr)
Value:
XV_HdmiRx1_ReadReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR2_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:197
#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a HDMI RX register.
Definition: xv_hdmirx1_hw.h:783

This macro reads the HDMI RX timer peripheral's remaining timer counter value.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_GetTmr2Value(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_GetTmr3Value (   InstancePtr)
Value:
XV_HdmiRx1_ReadReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR3_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:198
#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a HDMI RX register.
Definition: xv_hdmirx1_hw.h:783

This macro reads the HDMI RX timer peripheral's remaining timer counter value.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_GetTmr3Value(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_GetTmr4Value (   InstancePtr)
Value:
XV_HdmiRx1_ReadReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR4_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:199
#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a HDMI RX register.
Definition: xv_hdmirx1_hw.h:783

This macro reads the HDMI RX timer peripheral's remaining timer counter value.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_GetTmr4Value(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_GetVersion (   InstancePtr)
Value:
XV_HdmiRx1_ReadReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_VER_VERSION_OFFSET
VER Version Register offset.
Definition: xv_hdmirx1_hw.h:45
#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a HDMI RX register.
Definition: xv_hdmirx1_hw.h:783

This macro reads the RX version.

Parameters
InstancePtris a pointer to the XHdmi_RX core instance.
Returns
RX version.

*note C-style signature: u32 XV_HdmiRx1_GetVersion(XV_HdmiRx1 *InstancePtr)

#define XV_HDMIRX1_H_

Prevent circular inclusions by using protection macros.

#define XV_HdmiRx1_IsAudioActive (   InstancePtr)    (InstancePtr)->Stream.Audio.Active

This macro returns true is the audio stream is active else false.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
TRUE if the audio stream is active, FALSE if it is not.
Note
C-style signature: u32 XV_HdmiRx1_IsAudioActive(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_LinkEnable (   InstancePtr,
  SetClr 
)
Value:
{ \
if (SetClr) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HDMIRX1_PIO_OUT_LNK_EN_MASK
PIO Out video enable mask.
Definition: xv_hdmirx1_hw.h:113
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro asserts or clears the HDMI RX link enable.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
SetClrspecifies TRUE/FALSE value to either assert or release HDMI RX link enable.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Reset(XV_HdmiRx1 *InstancePtr, u8 SetClr)
#define XV_HdmiRx1_LinkIntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_LNKSTA_CTRL_IE_MASK
LNKSTA Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:460
#define XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET
LNKSTA Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:448
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro disable interrupt in the HDMI RX Link Status (LNKSTA) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_LinkIntrDisable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_LinkIntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_LNKSTA_CTRL_IE_MASK
LNKSTA Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:460
#define XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET
LNKSTA Control Register Set offset.
Definition: xv_hdmirx1_hw.h:447
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables interrupt in the HDMI RX Link Status (LNKSTA) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_LinkIntrEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_LnkstaDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET
LNKSTA Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:448
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK
LNKSTA Control Run mask.
Definition: xv_hdmirx1_hw.h:459

This macro disables the HDMI RX Link Status (LNKSTA) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_LinkstaDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_LnkstaEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET
LNKSTA Control Register Set offset.
Definition: xv_hdmirx1_hw.h:447
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK
LNKSTA Control Run mask.
Definition: xv_hdmirx1_hw.h:459

This macro enables the HDMI RX Link Status (LNKSTA) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_LinkstaEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_PioDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_CTRL_CLR_OFFSET
PIO Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:88
#define XV_HDMIRX1_PIO_CTRL_RUN_MASK
PIO Control Run mask.
Definition: xv_hdmirx1_hw.h:104

This macro disables the HDMI RX PIO peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_PioDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize(), and XV_HdmiRx1_Stop().

#define XV_HdmiRx1_PioEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_PIO_CTRL_SET_OFFSET
PIO Control Register Set offset.
Definition: xv_hdmirx1_hw.h:87
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_CTRL_RUN_MASK
PIO Control Run mask.
Definition: xv_hdmirx1_hw.h:104

This macro enables the HDMI RX PIO peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_PioEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_Start().

#define XV_HdmiRx1_PioIntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_PIO_CTRL_IE_MASK
PIO Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:105
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_CTRL_CLR_OFFSET
PIO Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:88

This macro disables interrupts in the HDMI RX PIO peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_PioIntrDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize(), and XV_HdmiRx1_Stop().

#define XV_HdmiRx1_PioIntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_PIO_CTRL_SET_OFFSET
PIO Control Register Set offset.
Definition: xv_hdmirx1_hw.h:87
#define XV_HDMIRX1_PIO_CTRL_IE_MASK
PIO Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:105
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables interrupts in the HDMI RX PIO peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_PioIntrEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_Start().

#define XV_HdmiRx1_Reset (   InstancePtr,
  Reset 
)
Value:
{ \
if (Reset) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HDMIRX1_PIO_OUT_RESET_MASK
PIO Out Reset mask.
Definition: xv_hdmirx1_hw.h:112
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro asserts or clears the HDMI RX reset.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies TRUE/FALSE value to either assert or release HDMI RX reset.
Returns
None.
Note
The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI link and video reset. C-style signature: void XV_HdmiRx1_Reset(XV_HdmiRx1 *InstancePtr, u8 Reset)
#define XV_HdmiRx1_SetAudioAcrUpdateEventEn (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg(InstancePtr->Config.BaseAddress, \
#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET
AUD Control Register Set offset.
Definition: xv_hdmirx1_hw.h:419
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK
AUD Control ACR Update Event Enable mask.
Definition: xv_hdmirx1_hw.h:428

This macro enables ACR Update Event in the HDMI RX Audio (AUD) peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.
#define XV_HdmiRx1_SetScrambler (   InstancePtr,
  SetClr 
)
Value:
{ \
if (SetClr) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(InstancePtr)->Stream.IsScrambled = (TRUE); \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(InstancePtr)->Stream.IsScrambled = (FALSE); \
} \
XV_HDMIRX1_SCDCFIELD_SCRAMBLER_STAT, \
SetClr); \
}
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
int XV_HdmiRx1_FrlDdcWriteField(XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)
This function writes the specified FRL SCDC Field.
Definition: xv_hdmirx1_frl.c:1394
#define XV_HDMIRX1_PIO_OUT_SCRM_MASK
PIO Out Scrambler mask.
Definition: xv_hdmirx1_hw.h:127
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro controls the HDMI RX Scrambler.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
SetClrspecifies TRUE/FALSE value to either enable or disable the scrambler.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_SetScrambler(XV_HdmiRx1 *InstancePtr, u8 SetClr)
#define XV_HdmiRx1_Tmr1Disable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR1_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:202
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr1Disable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr1Enable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR1_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:202
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr1Enable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr1IntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR1_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:203
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables interrupt in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr1IntrDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr1IntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR1_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:203

This macro enables interrupts in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_TmrIntrEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr1Start (   InstancePtr,
  Value 
)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMIRX1_TMR1_CNT_OFFSET), (u32)(Value))
#define XV_HDMIRX1_TMR1_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:196
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro starts the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr1Start(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_SetFrl10MicroSecondsTimer(), and XV_HdmiRx1_TmrStartMs().

#define XV_HdmiRx1_Tmr2Disable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR2_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:204
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr2Disable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr2Enable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HDMIRX1_TMR2_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:204
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr2Enable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr2IntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR2_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:205
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables interrupt in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr2IntrDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr2IntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HDMIRX1_TMR2_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:205
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables interrupts in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr2IntrEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr2Start (   InstancePtr,
  Value 
)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMIRX1_TMR2_CNT_OFFSET), (u32)(Value))
#define XV_HDMIRX1_TMR2_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:197
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro starts the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr2Start(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_TmrStartMs().

#define XV_HdmiRx1_Tmr3Disable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194
#define XV_HDMIRX1_TMR3_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:206

This macro disables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr3Disable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize(), and XV_HdmiRx1_Clear().

#define XV_HdmiRx1_Tmr3Enable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR3_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:206

This macro enables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr3Enable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr3IntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR3_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:207
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables interrupt in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr3IntrDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr3IntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HDMIRX1_TMR3_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:207
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables interrupts in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr3IntrEnable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr3Start (   InstancePtr,
  Value 
)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMIRX1_TMR3_CNT_OFFSET), (u32)(Value))
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR3_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:198

This macro starts the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr3Start(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_TmrStartMs().

#define XV_HdmiRx1_Tmr4Disable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR4_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:208
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr4Disable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr4Enable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR4_CTRL_RUN_MASK
TMR Control Run mask.
Definition: xv_hdmirx1_hw.h:208
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr4Enable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_Tmr4IntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR4_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:209
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET
TMR Control Register Clear offset.
Definition: xv_hdmirx1_hw.h:194

This macro disables interrupt in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr4IntrDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_Tmr4IntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET
TMR Control Register Set offset.
Definition: xv_hdmirx1_hw.h:193
#define XV_HDMIRX1_TMR4_CTRL_IE_MASK
TMR Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:209
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro enables interrupts in the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr4IntrEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_Tmr4Start (   InstancePtr,
  Value 
)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
(XV_HDMIRX1_TMR4_CNT_OFFSET), (u32)(Value))
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_TMR4_CNT_OFFSET
TMR Counter Register offset.
Definition: xv_hdmirx1_hw.h:199

This macro starts the HDMI RX timer peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Tmr4Start(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_TmrStartMs().

#define XV_HdmiRx1_VideoEnable (   InstancePtr,
  SetClr 
)
Value:
{ \
if (SetClr) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET
PIO Out Register Clear offset.
Definition: xv_hdmirx1_hw.h:92
#define XV_HDMIRX1_PIO_OUT_VID_EN_MASK
PIO Out video enable mask.
Definition: xv_hdmirx1_hw.h:114
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_PIO_OUT_SET_OFFSET
PIO Out Register Set offset.
Definition: xv_hdmirx1_hw.h:91

This macro asserts or clears the HDMI RX video enable.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
SetClrspecifies TRUE/FALSE value to either assert or release HDMI RX video enable.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_Reset(XV_HdmiRx1 *InstancePtr, u8 SetClr)
#define XV_HdmiRx1_VtdDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET
VTD Control Clear Register offset.
Definition: xv_hdmirx1_hw.h:223
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_VTD_CTRL_RUN_MASK
VTD Control Run mask.
Definition: xv_hdmirx1_hw.h:237

This macro disables the HDMI RX Timing Detector peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_VtdDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_VtdEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET
VTD Control Set Register offset.
Definition: xv_hdmirx1_hw.h:222
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_VTD_CTRL_RUN_MASK
VTD Control Run mask.
Definition: xv_hdmirx1_hw.h:237

This macro enables the HDMI RX Timing Detector peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_VtdEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_VtdIntrDisable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET
VTD Control Clear Register offset.
Definition: xv_hdmirx1_hw.h:223
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_VTD_CTRL_IE_MASK
VTD Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:238

This macro disables interrupt in the HDMI RX Timing Detector peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_VtdIntrDisable(XV_HdmiRx1 *InstancePtr)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_VtdIntrEnable (   InstancePtr)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET
VTD Control Set Register offset.
Definition: xv_hdmirx1_hw.h:222
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804
#define XV_HDMIRX1_VTD_CTRL_IE_MASK
VTD Control Interrupt Enable mask.
Definition: xv_hdmirx1_hw.h:238

This macro enables interrupt in the HDMI RX Timing Detector peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_VtdIntrEnable(XV_HdmiRx1 *InstancePtr)
#define XV_HdmiRx1_VtdSetTimebase (   InstancePtr,
  Value 
)
Value:
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
#define XV_HDMIRX1_VTD_CTRL_TIMEBASE_SHIFT
VTD Control timebase shift.
Definition: xv_hdmirx1_hw.h:242
#define XV_HDMIRX1_VTD_CTRL_OFFSET
VTD Control Register offset.
Definition: xv_hdmirx1_hw.h:221
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro sets the timebase in the HDMI RX Timing Detector peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
C-style signature: void XV_HdmiRx1_VtdSetTimebase(XV_HdmiRx1 *InstancePtr, Value)

Referenced by XV_HdmiRx1_CfgInitialize().

#define XV_HdmiRx1_VtdVfpEvent (   InstancePtr,
  SetClr 
)
Value:
{ \
if (SetClr) { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
else { \
XV_HdmiRx1_WriteReg((InstancePtr)->Config.BaseAddress, \
} \
}
#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET
VTD Control Set Register offset.
Definition: xv_hdmirx1_hw.h:222
#define XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK
VTD VFP change interrupt enable mask.
Definition: xv_hdmirx1_hw.h:241
#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET
VTD Control Clear Register offset.
Definition: xv_hdmirx1_hw.h:223
#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a HDMI RX register.
Definition: xv_hdmirx1_hw.h:804

This macro allow control to enable/disable the HDMI RX VFP event.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
SetClrspecifies TRUE/FALSE value to either enable or disable the VFP Event
Returns
None.
Note
C-style signature: void XV_HdmiRx1_VtdVfpEvent(XV_HdmiRx1 *InstancePtr, u8 SetClr)

Typedef Documentation

typedef void(* XV_HdmiRx1_Callback)(void *CallbackRef)

Callback type for interrupt.

Parameters
CallbackRefis a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.
Returns
None.
Note
None.

Enumeration Type Documentation

These constants specify different types of handler and used to differentiate interrupt requests from peripheral.

Enumerator
XV_HDMIRX1_HANDLER_CONNECT 

A connect event interrupt type.

XV_HDMIRX1_HANDLER_BRDG_OVERFLOW 

Interrupt type for bridge verflow.

XV_HDMIRX1_HANDLER_AUX 

Interrupt type for AUX peripheral.

XV_HDMIRX1_HANDLER_AUD 

Interrupt type for AUD peripheral.

XV_HDMIRX1_HANDLER_LNKSTA 

Interrupt type for LNKSTA peripheral.

XV_HDMIRX1_HANDLER_DDC 

Interrupt type for DDC peripheral.

XV_HDMIRX1_HANDLER_STREAM_DOWN 

Interrupt type for stream down.

XV_HDMIRX1_HANDLER_STREAM_INIT 

Interrupt type for stream init.

XV_HDMIRX1_HANDLER_STREAM_UP 

Interrupt type for stream up.

XV_HDMIRX1_HANDLER_HDCP 

Interrupt type for hdcp.

XV_HDMIRX1_HANDLER_DDC_HDCP_14_PROT 

Interrupt type for HDCP14PROT event.

XV_HDMIRX1_HANDLER_DDC_HDCP_22_PROT 

Interrupt type for HDCP22PROT event.

XV_HDMIRX1_HANDLER_LINK_ERROR 

Interrupt type for link error.

XV_HDMIRX1_HANDLER_SYNC_LOSS 

Interrupt type for sync loss.

XV_HDMIRX1_HANDLER_MODE 

Interrupt type for mode.

XV_HDMIRX1_HANDLER_TMDS_CLK_RATIO 

Interrupt type for TMDS clock ratio.

XV_HDMIRX1_HANDLER_VIC_ERROR 

Interrupt type for VIC error.

XV_HDMIRX1_HANDLER_PHY_RESET 

Handler for Configuration Retry Request.

XV_HDMIRX1_HANDLER_LNK_RDY_ERR 

Interrupt type for Link Ready error.

XV_HDMIRX1_HANDLER_VID_RDY_ERR 

Interrupt type for Video Ready error.

XV_HDMIRX1_HANDLER_SKEW_LOCK_ERR 

Interrupt type for Skew Lock error.

XV_HDMIRX1_HANDLER_FRL_CONFIG 

Handler for FRL Config.

XV_HDMIRX1_HANDLER_FRL_START 

Handler for FRL Start.

XV_HDMIRX1_HANDLER_TMDS_CONFIG 

Handler for TMDS.

XV_HDMIRX1_HANDLER_VFP_CHANGE 

Handler for VFP change event.

XV_HDMIRX1_HANDLER_VRR_RDY 

Handler for VRR rdy event.

XV_HDMIRX1_HANDLER_DYN_HDR 

Handler for Dynamic HDR.

XV_HDMIRX1_HANDLER_DSC_STRM_CH 

Handler type for DSC stream change event.

XV_HDMIRX1_HANDLER_DSC_PKT_ERR 

Handler type for DSC PPS Packet error event.

XV_HDMIRX1_HANDLER_DSC_STS_UPDT 

Handler type for SCDC Reg 0x10 bit 0 Status_Update bit set by HDMI Source.

Enumerator
XV_HDMIRX1_STATE_STREAM_DOWN 

Stream down.

XV_HDMIRX1_STATE_STREAM_IDLE 

Stream idle.

XV_HDMIRX1_STATE_STREAM_INIT 

Stream init.

XV_HDMIRX1_STATE_STREAM_ARM 

Stream arm.

XV_HDMIRX1_STATE_STREAM_LOCK 

Stream lock.

XV_HDMIRX1_STATE_STREAM_RDY 

Stream ready.

XV_HDMIRX1_STATE_STREAM_UP 

Stream up.

Enumerator
XV_HDMIRX1_SYNCSTAT_SYNC_LOSS 

Sync Loss.

XV_HDMIRX1_SYNCSTAT_SYNC_EST 

Sync Lock.

Function Documentation

int XV_HdmiRx1_CfgInitialize ( XV_HdmiRx1 InstancePtr,
XV_HdmiRx1_Config CfgPtr,
UINTPTR  EffectiveAddr 
)

This function initializes the HDMI RX core.

This function must be called prior to using the HDMI RX core. Initialization of the HDMI RX includes setting up the instance data, and ensuring the hardware is in a quiescent state.

Parameters
InstancePtris a pointer to the XHdmiRx1 core instance.
CfgPtrpoints to the configuration structure associated with the HDMI RX core.
EffectiveAddris the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.
Returns
  • XST_SUCCESS if XV_HdmiRx1_CfgInitialize was successful.
  • XST_FAILURE if HDMI RX PIO ID mismatched.
Note
None.

References XV_HdmiRx1::AudCallback, XV_HdmiRx1::AuxCallback, XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1::ConnectCallback, XV_HdmiRx1_Frl::CurFrlRate, XV_HdmiRx1::DdcCallback, XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Config::DSC, XV_HdmiRx1::FrlConfigCallback, XV_HdmiRx1::FrlStartCallback, XV_HdmiRx1::HdcpCallback, XV_HdmiRx1::HdcpRef, XV_HdmiRx1::IsReady, XV_HdmiRx1::LinkErrorCallback, XV_HdmiRx1::LnkStaCallback, XV_HdmiRx1::ModeCallback, XV_HdmiRx1::Stream, XV_HdmiRx1::StreamDownCallback, XV_HdmiRx1::StreamInitCallback, XV_HdmiRx1::StreamUpCallback, XV_HdmiRx1::SyncLossCallback, XV_HdmiRx1::TmdsClkRatioCallback, XV_HdmiRx1::TmdsConfigCallback, XV_HdmiRx1_AudioDisable, XV_HdmiRx1_AudioIntrEnable, XV_HdmiRx1_AuxDisable, XV_HdmiRx1_AuxFSyncVrrChEvtEnable, XV_HdmiRx1_AuxIntrEnable, XV_HdmiRx1_Clear(), XV_HdmiRx1_DdcDisable, XV_HdmiRx1_DdcEnable, XV_HdmiRx1_DdcScdcClear, XV_HdmiRx1_DdcScdcEnable, XV_HdmiRx1_FrlDdcWriteField(), XV_HdmiRx1_FrlReset(), XV_HdmiRx1_GetTime16Ms, XV_HdmiRx1_LnkstaDisable, XV_HdmiRx1_LnkstaEnable, XV_HDMIRX1_MASK_16, XV_HDMIRX1_PIO_ID, XV_HDMIRX1_PIO_ID_OFFSET, XV_HDMIRX1_PIO_IN_BRDG_OVERFLOW_MASK, XV_HDMIRX1_PIO_IN_DET_MASK, XV_HDMIRX1_PIO_IN_DSC_EN_STRM_CHG_EVT_MASK, XV_HDMIRX1_PIO_IN_DSC_PPS_PKT_ERR_MASK, XV_HDMIRX1_PIO_IN_EVT_FE_OFFSET, XV_HDMIRX1_PIO_IN_EVT_RE_OFFSET, XV_HDMIRX1_PIO_IN_LNK_RDY_MASK, XV_HDMIRX1_PIO_IN_MODE_MASK, XV_HDMIRX1_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK, XV_HDMIRX1_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK, XV_HDMIRX1_PIO_IN_VID_RDY_MASK, XV_HdmiRx1_PioDisable, XV_HdmiRx1_PioIntrDisable, XV_HdmiRx1_ReadReg, XV_HdmiRx1_SetFrlRateWrEvent_En(), XV_HdmiRx1_SetHpd(), XV_HDMIRX1_SHIFT_16, XV_HdmiRx1_Tmr1Disable, XV_HdmiRx1_Tmr1Enable, XV_HdmiRx1_Tmr1IntrDisable, XV_HdmiRx1_Tmr1IntrEnable, XV_HdmiRx1_Tmr2Disable, XV_HdmiRx1_Tmr2Enable, XV_HdmiRx1_Tmr2IntrDisable, XV_HdmiRx1_Tmr2IntrEnable, XV_HdmiRx1_Tmr3Disable, XV_HdmiRx1_Tmr3Enable, XV_HdmiRx1_Tmr3IntrDisable, XV_HdmiRx1_Tmr3IntrEnable, XV_HdmiRx1_Tmr4Disable, XV_HdmiRx1_Tmr4IntrDisable, XV_HdmiRx1_VtdDisable, XV_HdmiRx1_VtdIntrDisable, XV_HdmiRx1_VtdSetTimebase, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_Clear ( XV_HdmiRx1 InstancePtr)

This function clears the HDMI RX variables and sets them to the defaults.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
This is required after a reset or init.

References XV_HdmiRx1_AudioStream::Active, XV_HdmiRx1::AudCts, XV_HdmiRx1::AudFormat, XV_HdmiRx1::AudN, XV_HdmiRx1::Aux, XV_HdmiRx1_AudioStream::Channels, XV_HdmiRx1::IsErrorPrintCount, XV_HdmiRx1::Stream, XV_HdmiRx1::StreamDownCallback, XV_HdmiRx1::StreamDownRef, XV_HdmiRx1_Frl::TrainingState, XV_HDMIRX1_STATE_STREAM_DOWN, and XV_HdmiRx1_Tmr3Disable.

Referenced by XV_HdmiRx1_CfgInitialize().

void XV_HdmiRx1_ClearLinkStatus ( XV_HdmiRx1 InstancePtr)

This function clears the link error counters.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET, XV_HDMIRX1_LNKSTA_CTRL_ERR_CLR_MASK, XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

int XV_HdmiRx1_ConfigFrlLtpDetection ( XV_HdmiRx1 InstancePtr)

This function configures the link training pattern to be detected.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Status
  • XST_FAILURE
    • Source has not cleared FLT_update so sink should not update FLT_req and FLT_update as to ensure proper data handshake
    • XST_SUCCESS
    • Source has cleared FLT_update and sink has updated LTP_req and set FLT_update to 1
    • XST_NO_DATA
    • Source has cleared FLT_update but no update from sink is required
Note
None.

References XV_HdmiRx1::Config, XV_HdmiRx1_Frl::CurFrlRate, XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Frl::Ltp, XV_HdmiRx1::Stream, XV_HdmiRx1_Frl::TrainingState, XV_HdmiRx1_GetFrlLtpDetection(), XV_HdmiRx1_GetTmr1Value, XV_HdmiRx1_ResetFrlLtpDetection(), and XV_HdmiRx1_SetFrlLtpDetection().

u16 XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords ( XV_HdmiRx1 InstancePtr)

This function gets the number of bytes of the HDCP 2.2 read buffer in the DDC slave.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
  • HDCP 2.2 read buffer words
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_DDC_HDCP_STA_OFFSET, XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_MASK, XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_SHIFT, and XV_HdmiRx1_ReadReg.

u16 XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords ( XV_HdmiRx1 InstancePtr)

This function gets the number of bytes of the HDCP 2.2 write buffer in the DDC slave.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
  • HDCP 2.2 write buffer words
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_DDC_HDCP_STA_OFFSET, XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_MASK, XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_SHIFT, and XV_HdmiRx1_ReadReg.

u32 XV_HdmiRx1_DdcHdcpReadData ( XV_HdmiRx1 InstancePtr)

This function reads HDCP data from the DDC peripheral.

This is implemented as a function and not a macro, so the HDCP driver can bind the function call with a handler.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
Returns the HDCP data read from the DDC peripheral.
Note
C-style signature: u32 XHdmiRx1_DdcHdcpReadData(XHdmi_Rx *InstancePtr)

References XV_HDMIRX1_DDC_HDCP_DATA_OFFSET, and XV_HdmiRx1_ReadReg.

void XV_HdmiRx1_DdcHdcpSetAddress ( XV_HdmiRx1 InstancePtr,
u32  Address 
)

This function sets the HDCP address in the DDC peripheral.

This is implemented as a function and not a macro, so the HDCP driver can bind the function call with a handler.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Addressis the HDCP address.
Returns
None.
Note
C-style signature: void XHdmiRx1_DdcHdcpSetAddress(XHdmi_Rx *InstancePtr, u8 Address)

References XV_HDMIRX1_DDC_HDCP_ADDRESS_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_DdcHdcpWriteData ( XV_HdmiRx1 InstancePtr,
u32  Data 
)

This function writes HDCP data in the DDC peripheral.

This is implemented as a function and not a macro, so the HDCP driver can bind the function call with a handler.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Datais the HDCP data to be written.
Returns
None.
Note
C-style signature: void XHdmiRx1_DdcHdcpWriteData(XHdmi_Rx *InstancePtr, u8 Data)

References XV_HDMIRX1_DDC_HDCP_DATA_OFFSET, and XV_HdmiRx1_WriteReg.

int XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty ( XV_HdmiRx1 InstancePtr)

This function returns the status of the HDCP 2.2 read message buffer in the DDC slave.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
  • TRUE = HDCP 2.2 message buffer is empty.
  • FALSE = HDCP 2.2 message buffer contains data.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_DDC_HDCP_STA_OFFSET, XV_HDMIRX1_DDC_STA_HDCP_RMSG_EP_MASK, and XV_HdmiRx1_ReadReg.

int XV_HdmiRx1_DdcIsHdcpWriteMessageBufferEmpty ( XV_HdmiRx1 InstancePtr)

This function returns the status of the HDCP 2.2 write buffer in the DDC slave.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
  • TRUE = HDCP 2.2 message buffer is empty.
  • FALSE = HDCP 2.2 message buffer contains data.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_DDC_HDCP_STA_OFFSET, XV_HDMIRX1_DDC_STA_HDCP_WMSG_EP_MASK, and XV_HdmiRx1_ReadReg.

int XV_HdmiRx1_DdcLoadEdid ( XV_HdmiRx1 InstancePtr,
u8 *  EdidData,
u16  Length 
)

This function loads the EDID data into the DDC slave.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
EdidDatais a pointer to the EDID data array.
Lengthis the length, in bytes, of the EDID array.
Returns
  • XST_SUCCESS if the EDID data was loaded successfully
  • XST_FAILURE if the EDID data load failed
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_DDC_CTRL_EDID_EN_MASK, XV_HDMIRX1_DDC_CTRL_SET_OFFSET, XV_HDMIRX1_DDC_EDID_DATA_OFFSET, XV_HDMIRX1_DDC_EDID_WP_OFFSET, XV_HdmiRx1_DdcGetEdidWords(), and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_DdcRegDump ( XV_HdmiRx1 InstancePtr)

This function prints out RX's SCDC registers and values on STDIO/UART.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_SCDC_ADDR_MASK, XV_HDMIRX1_FRL_SCDC_DAT_SHIFT, XV_HDMIRX1_FRL_SCDC_OFFSET, XV_HDMIRX1_FRL_SCDC_RD_MASK, XV_HDMIRX1_FRL_SCDC_RDY_MASK, XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_DebugInfo ( XV_HdmiRx1 InstancePtr)

This function prints debug information on STDIO/UART console.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_MASK, XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_SHIFT, XV_HDMIRX1_DBG_STA_OFFSET, XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_MASK, XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_SHIFT, XV_HDMIRX1_DBG_STA_SKEW_LOCK_CHG_MASK, XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_MASK, XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_SHIFT, XV_HDMIRX1_DBG_STA_WA_TAP_CHGALL_MASK, XV_HDMIRX1_FRL_ERR_CNT1_OFFSET, XV_HDMIRX1_FRL_RATIO_ACT_OFFSET, XV_HDMIRX1_FRL_RATIO_TOT_OFFSET, XV_HDMIRX1_FRL_RSFC_CNT_OFFSET, XV_HDMIRX1_FRL_STA_FRL_LANES_MASK, XV_HDMIRX1_FRL_STA_FRL_MODE_MASK, XV_HDMIRX1_FRL_STA_FRL_RATE_MASK, XV_HDMIRX1_FRL_STA_FRL_RATE_SHIFT, XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_MASK, XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_SHIFT, XV_HDMIRX1_FRL_STA_OFFSET, XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_MASK, XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_SHIFT, XV_HDMIRX1_FRL_STA_SKEW_LOCK_MASK, XV_HDMIRX1_FRL_STA_STR_MASK, XV_HDMIRX1_FRL_STA_VID_LOCK_MASK, XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_MASK, XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_SHIFT, XV_HDMIRX1_FRL_VID_LOCK_CNT_OFFSET, XV_HdmiRx1_GetFrlActivePixRatio(), XV_HdmiRx1_GetFrlTotalPixRatio(), XV_HDMIRX1_LNKSTA_STA_OFFSET, XV_HDMIRX1_PIO_IN_ALIGNER_LOCK_MASK, XV_HDMIRX1_PIO_IN_MODE_MASK, XV_HDMIRX1_PIO_IN_OFFSET, XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_MASK, XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_SHIFT, XV_HDMIRX1_PKT_ECC_ERR_OFFSET, XV_HdmiRx1_ReadReg, XV_HDMIRX1_SR_SSB_ERR1_MASK, XV_HDMIRX1_SR_SSB_ERR2_MASK, XV_HDMIRX1_SR_SSB_ERR2_SHIFT, XV_HDMIRX1_SR_SSB_ERR_CNT0_OFFSET, XV_HDMIRX1_SR_SSB_ERR_CNT1_OFFSET, XV_HDMIRX1_SR_SSB_ERR_CNT2_OFFSET, XV_HDMIRX1_SR_SSB_ERR_CNT3_OFFSET, XV_HDMIRX1_TRIB_ANLZ_LN_ACT_ACT_SZ_MASK, XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_MASK, XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_SHIFT, XV_HDMIRX1_TRIB_ANLZ_LN_ACT_OFFSET, XV_HDMIRX1_TRIB_ANLZ_TIM_CHGD_CNT_MASK, XV_HDMIRX1_TRIB_ANLZ_TIM_HS_POL_MASK, XV_HDMIRX1_TRIB_ANLZ_TIM_OFFSET, XV_HDMIRX1_TRIB_ANLZ_TIM_VS_POL_MASK, XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_MASK, XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_SHIFT, XV_HDMIRX1_TRIB_HBP_HS_HS_SZ_MASK, XV_HDMIRX1_TRIB_HBP_HS_OFFSET, XV_HDMIRX1_VCKE_SYS_CNT_OFFSET, XV_HDMIRX1_VER_ID_OFFSET, and XV_HDMIRX1_VER_VERSION_OFFSET.

u32 XV_HdmiRx1_Divide ( u32  Dividend,
u32  Divisor 
)

This function calculates the divider for the frame calculation.

Parameters
Dividendis the dividend value to use in the calculation.
Divisoris the divisor value to use in the calculation.
Returns
The result of the calculation.
Note
None.
void XV_HdmiRx1_DynHDR_GetInfo ( XV_HdmiRx1 InstancePtr,
XV_HdmiRx1_DynHDR_Info RxDynHdrInfoPtr 
)

This function gets the Dynamic HDR packet type, length, whether graphics overlay and errors if any.

Parameters
InstancePtris a pointer to the XHdmiRx1 core instance.
RxDynHdrInfoPtris a pointer to XHdmiRx1 Dynamic HDR info instance.
Returns
None.
Note
None.

References XV_HdmiRx1::Config, XV_HdmiRx1_Config::DynamicHDR, XV_HDMIRX1_AUX_DYN_HDR_INFO_OFFSET, XV_HDMIRX1_AUX_DYN_HDR_STS_ERR_MASK, XV_HDMIRX1_AUX_DYN_HDR_STS_GOF_MASK, XV_HDMIRX1_AUX_DYN_HDR_STS_OFFSET, and XV_HdmiRx1_ReadReg.

void XV_HdmiRx1_DynHDR_SetAddr ( XV_HdmiRx1 InstancePtr,
u64  Addr 
)

This function sets the Dynamic HDR buffer address.

Parameters
InstancePtris a pointer to the XHdmiRx1 core instance.
Addris an address in 64bit format.
Returns
None.
Note
None.

References XV_HdmiRx1::Config, XV_HdmiRx1_Config::DynamicHDR, XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_LSB_OFFSET, XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_MSB_OFFSET, and XV_HdmiRx1_WriteReg.

int XV_HdmiRx1_ExecFrlState ( XV_HdmiRx1 InstancePtr)

This function executes the different of states of FRL.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1::Stream, and XV_HdmiRx1_Frl::TrainingState.

Referenced by XV_HdmiRx1_FrlLinkRetrain(), and XV_HdmiRx1_FrlModeEnable().

void XV_HdmiRx1_EXT_SYSRST ( XV_HdmiRx1 InstancePtr,
u8  Reset 
)

This function asserts or releases the HDMI RX External SYSRST.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies TRUE/FALSE value to either assert or release HDMI RX External SYSRST.
Returns
None.
Note
The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI External system reset. C-style signature: void XV_HdmiRx1_EXT_SYSRST(XV_HdmiRx1 *InstancePtr, u8 Reset)

References XV_HDMIRX1_PIO_OUT_CLR_OFFSET, XV_HDMIRX1_PIO_OUT_EXT_SYSRST_MASK, XV_HDMIRX1_PIO_OUT_SET_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_EXT_VRST ( XV_HdmiRx1 InstancePtr,
u8  Reset 
)

This function asserts or releases the HDMI RX External VRST.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies TRUE/FALSE value to either assert or release HDMI RX External VRST.
Returns
None.
Note
The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI external video reset. C-style signature: void XV_HdmiRx1_EXT_VRST(XV_HdmiRx1 *InstancePtr, u8 Reset)

References XV_HDMIRX1_PIO_OUT_CLR_OFFSET, XV_HDMIRX1_PIO_OUT_EXT_VRST_MASK, XV_HDMIRX1_PIO_OUT_SET_OFFSET, and XV_HdmiRx1_WriteReg.

u32 XV_HdmiRx1_FrlDdcReadField ( XV_HdmiRx1 InstancePtr,
XV_HdmiRx1_FrlScdcFieldType  Field 
)

This function reads the specified FRL SCDC Field.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Fieldspecifies the fields from SCDC channels to be written
Valuespecifies the values to be written
Returns
  • XST_SUCCESS
  • XST_FAILURE
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1_FrlScdcField::Offset, XV_HDMIRX1_FRL_SCDC_ADDR_MASK, XV_HDMIRX1_FRL_SCDC_DAT_SHIFT, XV_HDMIRX1_FRL_SCDC_OFFSET, XV_HDMIRX1_FRL_SCDC_RD_MASK, XV_HDMIRX1_FRL_SCDC_RDY_MASK, XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_FrlDdcWriteField(), XV_HdmiRx1_GetFrlLtpDetection(), XV_HdmiRx1_RetrieveFrlRateLanes(), and XV_HdmiRx1_UpdateEdFlags().

int XV_HdmiRx1_FrlDdcWriteField ( XV_HdmiRx1 InstancePtr,
XV_HdmiRx1_FrlScdcFieldType  Field,
u8  Value 
)

This function writes the specified FRL SCDC Field.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Fieldspecifies the fields from SCDC channels to be written
Valuespecifies the values to be written
Returns
  • XST_SUCCESS
  • XST_FAILURE
  • XST_DEVICE_BUSY
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1_FrlScdcField::Mask, XV_HdmiRx1_FrlScdcField::Shift, XV_HDMIRX1_FRL_SCDC_ADDR_MASK, XV_HDMIRX1_FRL_SCDC_DAT_MASK, XV_HDMIRX1_FRL_SCDC_DAT_SHIFT, XV_HDMIRX1_FRL_SCDC_OFFSET, XV_HDMIRX1_FRL_SCDC_RDY_MASK, XV_HDMIRX1_FRL_SCDC_WR_MASK, XV_HdmiRx1_FrlDdcReadField(), XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize(), XV_HdmiRx1_FrlReset(), XV_HdmiRx1_SetFrlLtpDetection(), and XV_HdmiRx1_UpdateEdFlags().

void XV_HdmiRx1_FrlLinkRetrain ( XV_HdmiRx1 InstancePtr,
u8  LtpThreshold,
XV_HdmiRx1_FrlLtp  DefaultLtp 
)

This function initiates FRL rate dropping procedure.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
LtpThresholdspecifies the number of times the LTP matching module must match against the incoming link training pattern before a match is indicated
DefaultLtpspecify the link training pattern which will be used for link training purposes
  • XV_HDMIRX1_LTP_LFSR0
  • XV_HDMIRX1_LTP_LFSR1
  • XV_HDMIRX1_LTP_LFSR2
  • XV_HDMIRX1_LTP_LFSR3
Returns
Status on if FrlTraining can be started or not.
Note
None.

References XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Frl::Ltp, XV_HdmiRx1::Stream, XV_HdmiRx1_Frl::TrainingState, XV_HdmiRx1_ExecFrlState(), and XV_HdmiRx1_SetFrlLtpThreshold().

void XV_HdmiRx1_FrlLtpDetectionDisable ( XV_HdmiRx1 InstancePtr)

This function disables the LTP detection module.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_FrlLtpDetectionEnable ( XV_HdmiRx1 InstancePtr)

This function enables the LTP detection module.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_CLR_OFFSET, XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_FrlModeEnable ( XV_HdmiRx1 InstancePtr,
u8  LtpThreshold,
XV_HdmiRx1_FrlLtp  DefaultLtp,
u8  FfeSuppFlag 
)

This function enables the FRL mode.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
LtpThresholdspecifies the number of times the LTP matching module must match against the incoming link training pattern before a match is indicated
DefaultLtpspecify the link training pattern which will be used for link training purposes
  • XV_HDMIRX1_LTP_LFSR0
  • XV_HDMIRX1_LTP_LFSR1
  • XV_HDMIRX1_LTP_LFSR2
  • XV_HDMIRX1_LTP_LFSR3
Returns
Status on if FrlTraining can be started or not.
Note
None.

References XV_HdmiRx1_Frl::DefaultLtp, XV_HdmiRx1_Frl::FfeSuppFlag, XV_HdmiRx1::Stream, XV_HdmiRx1_Frl::TrainingState, XV_HdmiRx1_ExecFrlState(), and XV_HdmiRx1_SetFrlLtpThreshold().

void XV_HdmiRx1_FrlReset ( XV_HdmiRx1 InstancePtr,
u8  Reset 
)

This function resets the FRL peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies if the FRL peripheral is under reset or not.
  • 0 = Reset released
  • 1 = Reset asserted
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_CLR_OFFSET, XV_HDMIRX1_FRL_CTRL_RSTN_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, XV_HdmiRx1_FrlDdcWriteField(), and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize(), and XV_HdmiRx1_SetHpd().

u32 XV_HdmiRx1_GetAcrCts ( XV_HdmiRx1 InstancePtr)

This function provides audio clock regenerating CTS (Cycle-Time Stamp) value at the HDMI sink device.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Audio clock CTS value.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_AUD_CTS_OFFSET, and XV_HdmiRx1_ReadReg.

u32 XV_HdmiRx1_GetAcrN ( XV_HdmiRx1 InstancePtr)

This function provides audio clock regenerating factor N value.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
ACR N value.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_AUD_N_OFFSET, and XV_HdmiRx1_ReadReg.

XVidC_ColorFormat XV_HdmiRx1_GetAviColorSpace ( XV_HdmiRx1 InstancePtr)

This function returns the AVI colorspace (captured by the AUX peripheral)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
The AVI colorspace value.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_AUX_STA_AVI_CS_MASK, XV_HDMIRX1_AUX_STA_AVI_CS_SHIFT, XV_HDMIRX1_AUX_STA_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_GetVideoProperties().

u8 XV_HdmiRx1_GetAviVic ( XV_HdmiRx1 InstancePtr)

This function returns the AVI VIC (captured by the AUX peripheral)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
The AVI VIC code.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_AUX_STA_AVI_VIC_MASK, XV_HDMIRX1_AUX_STA_AVI_VIC_SHIFT, XV_HDMIRX1_AUX_STA_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_GetVideoProperties().

u32 XV_HdmiRx1_GetFrlActivePixRatio ( XV_HdmiRx1 InstancePtr)

This function provides FRL Ratio (Active Pixel)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
FRL Clock Ratio (Active Pixel)
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_RATIO_ACT_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_DebugInfo().

u32 XV_HdmiRx1_GetFrlLtpDetection ( XV_HdmiRx1 InstancePtr,
u8  Lane 
)

This function returns the link training pattern to be detected for the selected lane.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Lanespecifies the lane of which the Link Training Pattern will be returned.
Returns
Link Training Pattern
  • 5 = LTP5 / LFSR 0
  • 6 = LTP6 / LFSR 1
  • 7 = LTP7 / LFSR 2
  • 8 = LTP8 / LFSR 3
Note
None.

References XV_HdmiRx1_FrlDdcReadField().

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

u32 XV_HdmiRx1_GetFrlTotalPixRatio ( XV_HdmiRx1 InstancePtr)

This function provides FRL Ratio (Total Pixel)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
FRL Clock Ratio (Total Pixel)
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_RATIO_TOT_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_DebugInfo().

XVidC_ColorDepth XV_HdmiRx1_GetGcpColorDepth ( XV_HdmiRx1 InstancePtr)

This function returns the GCP color depth (captured by the AUX peripheral)

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
The GCP color depth.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_AUX_STA_GCP_CD_MASK, XV_HDMIRX1_AUX_STA_GCP_CD_SHIFT, XV_HDMIRX1_AUX_STA_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_GetVideoProperties().

u32 XV_HdmiRx1_GetLinkStatus ( XV_HdmiRx1 InstancePtr,
u8  Type 
)

This function provides status of the HDMI RX core Link Status peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Typespecifies one of the type for which status to be provided:
  • 0 = Link error counter for channel 0.
  • 1 = Link error counter for channel 1.
  • 2 = Link error counter for channel 2.
Returns
Link status of the HDMI RX core link.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_LNKSTA_LNK_ERR0_OFFSET, and XV_HdmiRx1_ReadReg.

u32 XV_HdmiRx1_GetPatternsMatchStatus ( XV_HdmiRx1 InstancePtr)

This function returns the status of the patterns matched lanes.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_MASK, XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_SHIFT, XV_HDMIRX1_FRL_STA_OFFSET, and XV_HdmiRx1_ReadReg.

Referenced by XV_HdmiRx1_PhyResetPoll().

int XV_HdmiRx1_GetTmdsClockRatio ( XV_HdmiRx1 InstancePtr)

This function gets the SCDC TMDS clock ratio bit.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
  • TRUE = TMDS clock ratio bit is set.
  • FALSE = TMDS clock ratio bit is cleared.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_PIO_IN_OFFSET, XV_HDMIRX1_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK, and XV_HdmiRx1_ReadReg.

int XV_HdmiRx1_GetVideoProperties ( XV_HdmiRx1 InstancePtr)

This function reads the video properties from the aux peripheral.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1::Stream, XV_HDMIRX1_AUX_STA_AVI_MASK, XV_HDMIRX1_AUX_STA_OFFSET, XV_HdmiRx1_GetAviColorSpace(), XV_HdmiRx1_GetAviVic(), XV_HdmiRx1_GetGcpColorDepth(), and XV_HdmiRx1_ReadReg.

XV_HdmiC_VrrInfoframeType XV_HdmiRx1_GetVrrIfType ( XV_HdmiRx1 InstancePtr)

This function returns VRR infoframe type.

Parameters
InstancePtris a pointer to the XHdmiRx1 core instance.
Returns
XV_HdmiRx1_VrrInfoframeType
Note
None.

References XV_HdmiRx1::VrrIF.

void XV_HdmiRx1_Info ( XV_HdmiRx1 InstancePtr)

This function prints stream and timing information on STDIO/UART console.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
None.

References XV_HdmiRx1::Stream.

void XV_HdmiRx1_INT_LRST ( XV_HdmiRx1 InstancePtr,
u8  Reset 
)

This function asserts or releases the HDMI RX Internal LRST.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies TRUE/FALSE value to either assert or release HDMI RX Internal LRST.
Returns
None.
Note
The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI Internal link reset. C-style signature: void XV_HdmiRx1_INT_VRST(XV_HdmiRx1 *InstancePtr, u8 Reset)

References XV_HDMIRX1_PIO_OUT_CLR_OFFSET, XV_HDMIRX1_PIO_OUT_INT_LRST_MASK, XV_HDMIRX1_PIO_OUT_SET_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_INT_VRST ( XV_HdmiRx1 InstancePtr,
u8  Reset 
)

This function asserts or releases the HDMI RX Internal VRST.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Resetspecifies TRUE/FALSE value to either assert or release HDMI RX Internal VRST.
Returns
None.
Note
The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI Internal video reset. C-style signature: void XV_HdmiRx1_INT_VRST(XV_HdmiRx1 *InstancePtr, u8 Reset)

References XV_HDMIRX1_PIO_OUT_CLR_OFFSET, XV_HDMIRX1_PIO_OUT_INT_VRST_MASK, XV_HDMIRX1_PIO_OUT_SET_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_IntrHandler ( void *  InstancePtr)

This function is the interrupt handler for the HDMI RX driver.

This handler reads the pending interrupt from PIO, DDC, TIMDET, AUX, AUD and LNKSTA peripherals, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.

The application is responsible for connecting this function to the interrupt system. Application beyond this driver is also responsible for providing callbacks to handle interrupts and installing the callbacks using XV_HdmiRx1_SetCallback() during initialization phase. An example delivered with this driver demonstrates how this could be done.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 instance that just interrupted.
Returns
None.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1::IsReady, XV_HDMIRX1_AUD_STA_IRQ_MASK, XV_HDMIRX1_AUD_STA_OFFSET, XV_HDMIRX1_AUX_STA_IRQ_MASK, XV_HDMIRX1_AUX_STA_OFFSET, XV_HDMIRX1_DDC_STA_IRQ_MASK, XV_HDMIRX1_DDC_STA_OFFSET, XV_HDMIRX1_FRL_STA_IRQ_MASK, XV_HDMIRX1_FRL_STA_OFFSET, XV_HDMIRX1_LNKSTA_STA_IRQ_MASK, XV_HDMIRX1_LNKSTA_STA_OFFSET, XV_HDMIRX1_PIO_STA_IRQ_MASK, XV_HDMIRX1_PIO_STA_OFFSET, XV_HdmiRx1_ReadReg, XV_HDMIRX1_TMR_STA_IRQ_MASK, XV_HDMIRX1_TMR_STA_OFFSET, XV_HDMIRX1_VTD_STA_IRQ_MASK, and XV_HDMIRX1_VTD_STA_OFFSET.

int XV_HdmiRx1_IsLinkStatusErrMax ( XV_HdmiRx1 InstancePtr)

This function provides status of one of the link error counters reached the maximum value.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
  • TRUE = Maximum error counter reached.
  • FALSE = Maximum error counter not reached.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_LNKSTA_STA_ERR_MAX_MASK, XV_HDMIRX1_LNKSTA_STA_OFFSET, and XV_HdmiRx1_ReadReg.

int XV_HdmiRx1_IsStreamConnected ( XV_HdmiRx1 InstancePtr)

This function provides the stream connected status.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
  • TRUE = Stream is connected.
  • FALSE = Stream is connected.
Note
None.

References XV_HdmiRx1::Stream.

int XV_HdmiRx1_IsStreamScrambled ( XV_HdmiRx1 InstancePtr)

This function provides the stream scrambler status.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
  • TRUE = Stream is scrambled.
  • FALSE = Stream is not scrambled.
Note
None.

References XV_HdmiRx1::Stream.

int XV_HdmiRx1_IsStreamUp ( XV_HdmiRx1 InstancePtr)

This function provides status of the stream.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
  • TRUE = Stream is up.
  • FALSE = Stream is down.
Note
None.

References XV_HdmiRx1::Stream, and XV_HDMIRX1_STATE_STREAM_UP.

XV_HdmiRx1_Config* XV_HdmiRx1_LookupConfig ( u16  DeviceId)

This function returns a reference to an XV_HdmiRx1_Config structure based on the core id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xv_hdmirx1_g.c file.

Parameters
DeviceIdis the unique core ID of the HDMI RX core for the lookup operation.
Returns
XV_HdmiRx1_LookupConfig returns a reference to a config record in the configuration table (in xv_hdmirx1_g.c) corresponding to DeviceId, or NULL if no match is found.
Note
None.
XVidC_VideoMode XV_HdmiRx1_LookupVmId ( u8  Vic)

This function searches for the video mode based on the vic.

Parameters
Vic
Returns
Vic defined in the VIC table.
Note
None.
void XV_HdmiRx1_PhyResetPoll ( XV_HdmiRx1 InstancePtr)

This function polls the pattern matching status and decide if the Phy needs to be reset or not.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Frl::Lanes, XV_HdmiRx1::PhyResetCallback, XV_HdmiRx1::PhyResetRef, XV_HdmiRx1::Stream, XV_HdmiRx1_GetPatternsMatchStatus(), and XV_HdmiRx1_TmrStartMs().

void XV_HdmiRx1_RegisterDebug ( XV_HdmiRx1 InstancePtr)

This function prints out HDMI RX register.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_VID_LOCK_CNT_OFFSET, and XV_HdmiRx1_ReadReg.

void XV_HdmiRx1_ResetFrlLtpDetection ( XV_HdmiRx1 InstancePtr)

This function reset the link training pattern for the specified lane.

This is needed whenever the link training pattern is changed or the RxFFE is changed.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Lanespecifies the lane of which the Link Training Pattern will be detected for.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_CLR_OFFSET, XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

int XV_HdmiRx1_RetrieveFrlRateLanes ( XV_HdmiRx1 InstancePtr)

This function updates the software's FRL Rate and FRL Lanes by reading and decoding the information from the RX core.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Frl::CurFrlRate, XV_HdmiRx1_Frl::Lanes, XV_HdmiRx1_Frl::LineRate, XV_HdmiRx1::Stream, and XV_HdmiRx1_FrlDdcReadField().

int XV_HdmiRx1_SelfTest ( XV_HdmiRx1 InstancePtr)

This function reads ID of PIO peripheral.

Parameters
InstancePtris a pointer to the HDMI RX core instance.
Returns
  • XST_SUCCESS if PIO ID was matched.
  • XST_FAILURE if PIO ID was mismatched.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_MASK_16, XV_HDMIRX1_PIO_ID, XV_HDMIRX1_PIO_ID_OFFSET, XV_HdmiRx1_ReadReg, and XV_HDMIRX1_SHIFT_16.

void XV_HdmiRx1_SetAxiClkFreq ( XV_HdmiRx1 InstancePtr,
u32  ClkFreq 
)

This function sets the AXI4-Lite Clock Frequency.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
ClkFreqspecifies the value that needs to be set.
Returns
Note
This is required after a reset or init.

References XV_HdmiRx1::Config.

int XV_HdmiRx1_SetCallback ( XV_HdmiRx1 InstancePtr,
XV_HdmiRx1_HandlerType  HandlerType,
void *  CallbackFunc,
void *  CallbackRef 
)

This function installs an asynchronous callback function for the given HandlerType:

HandlerType                 Callback Function Type
-------------------------   -----------------------------------------------
(XV_HDMIRX1_HANDLER_VTD)      VtdCallback
(XV_HDMIRX1_HANDLER_AUX)      AuxCallback
(XV_HDMIRX1_HANDLER_AUD)      AudCallback
(XV_HDMIRX1_HANDLER_LNKSTA)   LnkStaCallback
(XV_HDMIRX1_HANDLER_PIO)      PioCallback
Parameters
InstancePtris a pointer to the HDMI RX core instance.
HandlerTypespecifies the type of handler.
CallbackFuncis the address of the callback function.
CallbackRefis a user data item that will be passed to the callback function when it is invoked.
Returns
  • XST_SUCCESS if callback function installed successfully.
  • XST_INVALID_PARAM when HandlerType is invalid.
Note
Invoking this function for a handler that already has been installed replaces it with the new handler.

References XV_HdmiRx1::AudCallback, XV_HdmiRx1::AudRef, XV_HdmiRx1::AuxCallback, XV_HdmiRx1::AuxRef, XV_HdmiRx1::BrdgOverflowCallback, XV_HdmiRx1::BrdgOverflowRef, XV_HdmiRx1::ConnectCallback, XV_HdmiRx1::ConnectRef, XV_HdmiRx1::DdcCallback, XV_HdmiRx1::DdcRef, XV_HdmiRx1::DSCPktErrCallback, XV_HdmiRx1::DSCPktErrRef, XV_HdmiRx1::DSCStreamChangeEventCallback, XV_HdmiRx1::DSCStrmChgEvtRef, XV_HdmiRx1::DSCStsUpdtEvtCallback, XV_HdmiRx1::DSCStsUpdtEvtRef, XV_HdmiRx1::DynHdrCallback, XV_HdmiRx1::DynHdrRef, XV_HdmiRx1::FrlConfigCallback, XV_HdmiRx1::FrlConfigRef, XV_HdmiRx1::FrlLts1Callback, XV_HdmiRx1::FrlLts1Ref, XV_HdmiRx1::FrlLts2Callback, XV_HdmiRx1::FrlLts2Ref, XV_HdmiRx1::FrlLts3Callback, XV_HdmiRx1::FrlLts3Ref, XV_HdmiRx1::FrlLts4Callback, XV_HdmiRx1::FrlLts4Ref, XV_HdmiRx1::FrlLtsLCallback, XV_HdmiRx1::FrlLtsLRef, XV_HdmiRx1::FrlLtsPCallback, XV_HdmiRx1::FrlLtsPRef, XV_HdmiRx1::FrlStartCallback, XV_HdmiRx1::FrlStartRef, XV_HdmiRx1::Hdcp14ProtEvtCallback, XV_HdmiRx1::Hdcp14ProtEvtRef, XV_HdmiRx1::Hdcp22ProtEvtCallback, XV_HdmiRx1::Hdcp22ProtEvtRef, XV_HdmiRx1::HdcpCallback, XV_HdmiRx1::HdcpRef, XV_HdmiRx1::LinkErrorCallback, XV_HdmiRx1::LinkErrorRef, XV_HdmiRx1::LnkRdyErrorCallback, XV_HdmiRx1::LnkRdyErrorRef, XV_HdmiRx1::LnkStaCallback, XV_HdmiRx1::LnkStaRef, XV_HdmiRx1::ModeCallback, XV_HdmiRx1::ModeRef, XV_HdmiRx1::PhyResetCallback, XV_HdmiRx1::PhyResetRef, XV_HdmiRx1::SkewLockErrorCallback, XV_HdmiRx1::SkewLockErrorRef, XV_HdmiRx1::StreamDownCallback, XV_HdmiRx1::StreamDownRef, XV_HdmiRx1::StreamInitCallback, XV_HdmiRx1::StreamInitRef, XV_HdmiRx1::StreamUpCallback, XV_HdmiRx1::StreamUpRef, XV_HdmiRx1::SyncLossCallback, XV_HdmiRx1::SyncLossRef, XV_HdmiRx1::TmdsClkRatioCallback, XV_HdmiRx1::TmdsClkRatioRef, XV_HdmiRx1::TmdsConfigCallback, XV_HdmiRx1::TmdsConfigRef, XV_HdmiRx1::VfpChangeCallback, XV_HdmiRx1::VfpChangeRef, XV_HdmiRx1::VicErrorCallback, XV_HdmiRx1::VicErrorRef, XV_HdmiRx1::VidRdyErrorCallback, XV_HdmiRx1::VidRdyErrorRef, XV_HdmiRx1::VrrRdyCallback, XV_HdmiRx1::VrrRdyRef, XV_HDMIRX1_HANDLER_AUD, XV_HDMIRX1_HANDLER_AUX, XV_HDMIRX1_HANDLER_BRDG_OVERFLOW, XV_HDMIRX1_HANDLER_CONNECT, XV_HDMIRX1_HANDLER_DDC, XV_HDMIRX1_HANDLER_DDC_HDCP_14_PROT, XV_HDMIRX1_HANDLER_DDC_HDCP_22_PROT, XV_HDMIRX1_HANDLER_DSC_PKT_ERR, XV_HDMIRX1_HANDLER_DSC_STRM_CH, XV_HDMIRX1_HANDLER_DSC_STS_UPDT, XV_HDMIRX1_HANDLER_DYN_HDR, XV_HDMIRX1_HANDLER_FRL_CONFIG, XV_HDMIRX1_HANDLER_FRL_START, XV_HDMIRX1_HANDLER_HDCP, XV_HDMIRX1_HANDLER_LINK_ERROR, XV_HDMIRX1_HANDLER_LNK_RDY_ERR, XV_HDMIRX1_HANDLER_LNKSTA, XV_HDMIRX1_HANDLER_MODE, XV_HDMIRX1_HANDLER_PHY_RESET, XV_HDMIRX1_HANDLER_SKEW_LOCK_ERR, XV_HDMIRX1_HANDLER_STREAM_DOWN, XV_HDMIRX1_HANDLER_STREAM_INIT, XV_HDMIRX1_HANDLER_STREAM_UP, XV_HDMIRX1_HANDLER_SYNC_LOSS, XV_HDMIRX1_HANDLER_TMDS_CLK_RATIO, XV_HDMIRX1_HANDLER_TMDS_CONFIG, XV_HDMIRX1_HANDLER_VFP_CHANGE, XV_HDMIRX1_HANDLER_VIC_ERROR, XV_HDMIRX1_HANDLER_VID_RDY_ERR, and XV_HDMIRX1_HANDLER_VRR_RDY.

void XV_HdmiRx1_SetColorFormat ( XV_HdmiRx1 InstancePtr)

This function sets the color format.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1::Stream, XV_HDMIRX1_PIO_OUT_COLOR_SPACE_MASK, XV_HDMIRX1_PIO_OUT_COLOR_SPACE_SHIFT, XV_HDMIRX1_PIO_OUT_MSK_OFFSET, XV_HDMIRX1_PIO_OUT_OFFSET, and XV_HdmiRx1_WriteReg.

void XV_HdmiRx1_SetFrl10MicroSecondsTimer ( XV_HdmiRx1 InstancePtr)

This function sets the timer of RX Core's FRL peripheral for 10 Microseconds.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
None.
Returns
None.
Note
None.

References XV_HdmiRx1::Config, and XV_HdmiRx1_Tmr1Start.

void XV_HdmiRx1_SetFrlLtpDetection ( XV_HdmiRx1 InstancePtr,
u8  Lane,
XV_HdmiRx1_FrlLtpType  Ltp 
)

This function sets the link training pattern to be detected for the selected lane.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Lanespecifies the lane of which the Link Training Pattern will be detected for.
Ltpspecifies Link Training Pattern
  • 5 = LTP5 / LFSR 0
  • 6 = LTP6 / LFSR 1
  • 7 = LTP7 / LFSR 2
  • 8 = LTP8 / LFSR 3
Returns
Note
None.

References XV_HdmiRx1_FrlDdcWriteField().

Referenced by XV_HdmiRx1_ConfigFrlLtpDetection().

void XV_HdmiRx1_SetFrlLtpThreshold ( XV_HdmiRx1 InstancePtr,
u8  Threshold 
)

This function sets the number of times the full link training patterns need to be matched before it is considered as a lock.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Thresholdspecifies the number of times the full link training patterns need to be matched.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_FLT_THRES_MASK, XV_HDMIRX1_FRL_CTRL_FLT_THRES_SHIFT, XV_HDMIRX1_FRL_CTRL_OFFSET, XV_HdmiRx1_ReadReg, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_FrlLinkRetrain(), and XV_HdmiRx1_FrlModeEnable().

void XV_HdmiRx1_SetFrlRateWrEvent_En ( XV_HdmiRx1 InstancePtr)

This function sets the FRL rate write enable Event.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HDMIRX1_FRL_CTRL_FRL_RATE_WR_EVT_EN_MASK, XV_HDMIRX1_FRL_CTRL_SET_OFFSET, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize().

int XV_HdmiRx1_SetHpd ( XV_HdmiRx1 InstancePtr,
u8  SetClr 
)

This function enables/clear Hot-Plug-Detect.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
SetClrspecifies TRUE/FALSE value to either enable or clear HPD respectively.
Returns
  • XST_SUCCESS is always returned.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1_FrlReset(), XV_HDMIRX1_PIO_OUT_CLR_OFFSET, XV_HDMIRX1_PIO_OUT_HPD_MASK, XV_HDMIRX1_PIO_OUT_SET_OFFSET, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_CfgInitialize().

void XV_HdmiRx1_SetPixelClk ( XV_HdmiRx1 InstancePtr)

This function sets the PixelClk based on the current ColorDepth, RefClk and ColorFormatId.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.

References XV_HdmiRx1::Stream.

int XV_HdmiRx1_SetPixelRate ( XV_HdmiRx1 InstancePtr)

This function sets the pixel rate.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
  • XST_SUCCESS is always returned.
Note
None.

References XV_HdmiRx1_Config::BaseAddress, XV_HdmiRx1::Config, XV_HdmiRx1::Stream, XV_HDMIRX1_PIO_OUT_MSK_OFFSET, XV_HDMIRX1_PIO_OUT_OFFSET, XV_HDMIRX1_PIO_OUT_PIXEL_RATE_MASK, XV_HDMIRX1_PIO_OUT_PIXEL_RATE_SHIFT, and XV_HdmiRx1_WriteReg.

Referenced by XV_HdmiRx1_SetStream().

int XV_HdmiRx1_SetStream ( XV_HdmiRx1 InstancePtr,
XVidC_PixelsPerClock  Ppc,
u32  Clock 
)

This function sets the HDMI RX stream parameters.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Ppcspecifies the pixel per clock.
  • 4 = XVIDC_PPC_4
Clockspecifies reference pixel clock frequency.
Returns
  • XST_SUCCESS is always returned.
Note
None.

References XV_HdmiRx1::Stream, and XV_HdmiRx1_SetPixelRate().

void XV_HdmiRx1_SetVrrIfType ( XV_HdmiRx1 InstancePtr,
XV_HdmiC_VrrInfoframeType  Type 
)

This function Sets VRR infoframe type.

Parameters
InstancePtris a pointer to the XHdmiRx1 core instance.
Typeof type XV_HdmiRx1_VrrInfoframeType
Returns
None.
Note
None.

References XV_HdmiRx1::VrrIF.

void XV_HdmiRx1_Start ( XV_HdmiRx1 InstancePtr)

This function starts the HDMI RX core.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
This is required after a reset or initialization.

References XV_HdmiRx1_PioEnable, and XV_HdmiRx1_PioIntrEnable.

void XV_HdmiRx1_Stop ( XV_HdmiRx1 InstancePtr)

This function stops the HDMI RX core.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.

References XV_HdmiRx1_PioDisable, and XV_HdmiRx1_PioIntrDisable.

void XV_HdmiRx1_TmrStartMs ( XV_HdmiRx1 InstancePtr,
u32  Milliseconds,
u8  TimerSelect 
)

This function sets the timer of RX Core.

Parameters
InstancePtris a pointer to the XHdmi_Rx core instance.
Millisecondsspecifies the timer's frequency (in milliseconds)
TimerSelectselects which of the timer unit to be used
Returns
None.
Note
None.

References XV_HdmiRx1::Config, XV_HdmiRx1_Tmr1Start, XV_HdmiRx1_Tmr2Start, XV_HdmiRx1_Tmr3Start, and XV_HdmiRx1_Tmr4Start.

Referenced by XV_HdmiRx1_PhyResetPoll().

void XV_HdmiRx1_UpdateEdFlags ( XV_HdmiRx1 InstancePtr)

This function checks if RX's CED or RSED counters are incrementing at the rate of 4 or higher per second or if they first hit the maximum value (0x7FFF) then set the CED_Update or RSED_Update SCDC flags if true.

Parameters
InstancePtris a pointer to the XV_HdmiRx1 core instance.
Returns
None.
Note
This function needs to be called every 1 second to comply with the spec on CED_Update and RSED_Update flags updating.

References XV_HdmiRx1::Stream, XV_HdmiRx1_FrlDdcReadField(), and XV_HdmiRx1_FrlDdcWriteField().